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Programming Details
Interrupt Handling
2
Serial
Interrupt
No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
2-2
The MVME 2100 uses the Embedded Programmable Interrupt Controller
(EPIC) integrated into the processor to manage locally generated
interrupts. The interrupt controller will operate in the serial interrupt mode.
Currently defined external interrupting devices and serial interrupt
assignments are shown in the table below:
Table 2-1. Serial Interrupt Assignments
Edge/
Polarity Interrupt Source
Level
N/A
N/A
Not Used
Level
Low
DEC21143 Controller
Level
Low
PMC/PC-MIP Type I Slot 0
Level
Low
PC-MIP Type I Slot 1
Level
Low
PC-MIP Type II Slot 0
Level
Low
PC-MIP Type II Slot 1
N/A
N/A
Not Used
Level
Low
PCI Expansion Interrupt A/Universe II (LINT0)
Level
Low
PCI Expansion Interrupt B/Universe II (LINT1)
Level
Low
PCI Expansion Interrupt C/Universe II (LINT2)
Level
Low
PCI Expansion Interrupt D/Universe II (LINT3)
N/A
N/A
Not Used
N/A
N/A
Not Used
Level
High
16550 UART
Edge
Low
Front panel Abort Switch
Level
Low
RTC IRQ
Notes 1. Interrupts 0, 6, 11, and 12 are not used and should be
disabled by setting the priority to zero in processor's Serial
Interrupt Source/Vector Priority Registers.
2. Interrupts 7-10 are shared between the PCI INTA-D and
the Universe II VMEbus local interrupts 0-3 as shown.
Universe II local interrupts 4-7 are not used.
Computer Group Literature Center Web Site
Notes
1
1
2
2
2
2
1
1
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