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Operating Instructions
2
Interrupt Handling
2-6
❏
DEC 21140 Ethernet Controller
❏
PMC Slot (PCI mezzanine card)
The arbitration for these six bus mastering devices is provided by custom
onboard hardware. This arbiter implements a rotating priority scheme in
which the last master granted becomes the lowest priority. The order of
rotation is shown in the list above.
The Raven ASIC provides an MPIC Interrupt Controller to handle various
interrupt sources. It controls PHB (PCI Host Bridge) MPU/local bus
interface functions on the MCP750HA, as well as performing interrupt
handling. Sources of interrupts may be any of the following:
❏
The Raven ASIC itself (timer interrupts or transfer error interrupts)
❏
The processor (processor self-interrupts)
❏
The Falcon chip set (memory error interrupts)
❏
The PCI bus (interrupts from PCI devices)
❏
The CompactPCI bus (interrupts from CompactPCI devices)
❏
The CompactPCI expansion bus (interrupts from HSC and
expansion bus)
❏
Power monitor interrupts
❏
Watchdog timer interrupt
❏
The ISA bus (interrupts from ISA devices)
For details on interrupt handling, refer to the MPC750 Single Board
Computer Programmer's Reference Guide. For details on chassis interrupt
routing, refer to the chassis documentation that applies to the specific
model you are using. Refer to
list of those documents.
Appendix C, Related
Documentation, for a
Computer Group Literature Center Web Site
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