Commodore Amiga A500 Technical Reference Manual page 99

THE B2000
COPROCESSOR
INTERFACE
Normal 68000 DMA
Architecture
Where the 68000 DMA
Protocol Fails
The B2000 computer implements an extended version of the
A2000's Coprocessor Slot, designed to make the swapping of main
processors under program control much more powerful and trans-
parent to the rest of the B2000 system. There are things that can
be done from the B2000 Coprocessor slot that can't be done from
the A2000's Coprocessor Slot, so this is an important consideration
to anyone designing a Coprocessor device of some kind.
The 68000 supports hardware signals designed to permit a simple
DMA protocol. This protocol allows multiple devices to take control
of the 68000's data, address, and control buses. When a device of
some kind desires direct access to the 68000's bus, it asserts the
/BR (Bus Request) input of the 68000. Once /BR is asserted, the
68000 will complete whatever operation it's doing to the point it
can cleanly relinquish its bus. At this point, it will assert its /BG (Bus
Grant) output, telling the device requesting DMA that it's just about
ready to shut down. The requesting device then issues /BGACK (Bus
Grant Acknowledge) as soon as the 68000 is completely off the bus
(DTACK and /AS are negated). When the DMAing device is done with
the bus. it releases /DTACK and /BR. and the 68000 will then
release /BG.
The above protocol, as implemented in the 68000, is sufficient for
many types of DMA operation, especially for simple things in which
there are single DMA devices on the bus. What this doesn't easily ac-
count for are multiple DMA devices. While the /BR and /BGACK in-
puts to the 68000 can be wire-ORed to support several devices,
there are still problems with this scheme. Should multiple devices re-
quest DMA at the same time, the 68000 will see nothing different
than if only one device is requesting DMA. While careful monitoring
of the /BGACK by responding potential bus masters can solve some
of the problems, there are much cleaner approaches to this problem.
One such solution is implemented in the ZORRO and A2000/B2000
Expansion Buses. Each slot on the Expansion Bus has its own private
Bus Request and Bus Grant. Each Bus Request signal is considered
by a priority encoding and latching circuit. The result is that if
simultaneous Bus Requests come in from Expansion Slots, only the
Slot given higher priority will actually get a Bus Grant. Any Bus
Requests that come in while another DMA is in effect are held off
until the 68000's/BG line has been negated for at least one tick, this
circuitry, part of the original ZORRO specification, eliminates the
problems that can occur with various DMA devices all competing for
the Expansion and Local Buses.
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