Commodore Amiga A500 Technical Reference Manual page 193

PIN PIN
NAME NUMBER
A19-A1 59 thru 77
RD15-RD0 1 thru 14
and 83 & 84
AS* 24
RGEN* 23
PRW 22
RRW 21
RRW 21
Table 6-1 Pin Description
SIGNAL
DIRECTION DESCRIPTION
IN Address bus—A1 to A8 are used by the processor to
select the internal registers and put an address code
on the RGA lines to select registers outside the
device.
The processor uses Al to At 8 to generate multi-
plexed DRAM addresses on the MA outputs. The Al 9
line is used to indicate which RAS line is activated. If
A19 is high, RAS1 * is asserted; if low. RASO* is as-
serted.
I/O This data bus is buffered and is used by the
processor to access the device registers. The data bus
is also accessed during DMA operations.
IN Active low. This input is the processor address strobe
signal. When asserted, it indicates that the address
lines (Al to A19) are valid.
IN Active low. When this signal is asserted along with
AS*, the processor uses Al to A8 to access one of the
device registers or put a value on the RGA outputs to
select registers outside the device.
IN Active low. When this signal is asserted together with
AS*, the processor is doing a DRAM access. The pro-
cessor supplies an address on the Al to A18 inputs
and the device multiplexes this address onto the MA
outputs; during the same cycle, the processor con-
trols the A19 line to select one of the RAS lines.
IN This signal defines the data bus transfer as a read or
write cycle to memory. The signal is only enabled
when the processor is undergoing a DRAM access. A
low on this signal signifies a processor write cycle to
memory: a high indicates a processor read cycle from
memory.
OUT The device controls this signal to indicate either a
DMA or processor DRAM read/write access. In both
cases, a low on this line indicates a write operation
and a high indicates a read operation.
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