Commodore Amiga A500 Technical Reference Manual page 210

These registers control the horizontal tinning of the beginning and
end of the Bit Plane DMA display data fetch. The vertical Bit Plane
DMA timing is identical to the Display windows described above. The
Bit Plane Modulos are dependent on the Bit Plane horizontal size,
and on this data fetch window size.
Register bit assignment
BIT# 15,14,13,12,11,10,09,08.07.06,05,04,03,02,01,00
USE XXXXXXXXHBH7H6H5H4H3XX
(X bits should always be driven with 0 to maintain upward com-
patibility)
The tables below show the start and stop timing for different regis-
ter contents.
DDFSTRT (Left edge of display data fetch)
PURPOSE
Extra wide (max) *
wide
normal
narrow
DDFSTOP (Right edge of display data fetch)
PURPOSE
narrow
normal
wide (max)
DMACON
DMACONR
This register controls all of the DMA channels, and contains Blitter
DMA status bits.
BIT# FUNCTION
15 SET/CLR
14 BBUSY
13 BZERO
12 X
11 X
10 BLTPRI
207
H8, H7, H6, H5, H4
0 0 1
0 0 1
0 0 1
0 1 0
H8, H7, H6, H5, H4,
1 1 0
1 1 0
1 1 0
DMA control write (clear or set)
DMA control (and Blitter status) read
DESCRIPTION
Set/Clear control bit. Determines if bits
written with a 1 get set or cleared.
Blitter busy status bit (read only)
Blitter logic zero status bit (read only)
Blitter DMA priority (over CPU micro)
—also called "Blitter Nasty"
—disables /BLS pin, preventing micro
from stealing any bus cycles while blitter
DMA is running.
0 1
1 0
1 1
0 0
0 1
1 0
1 1