Commodore Amiga A500 Technical Reference Manual page 175

Step 3: Reading The
Command Block
Step 4: Data Block
Transfer
Step 5: Command
Completion
COMMANDS
Command Block
contains EO or AO, before attempting to clear the FIFO and retrans-
mit the block of data, if necesssary. If the FIFO cannot be cleared
after within 20 mS, the command will be terminated in the normal
manner, if possible.
If byte 12 is an FF, the rest of the command block is retrieved by
the CMD. This requires the execution of Step 1 (LDO only) followed
by Step 2 four times. The data value for state DE of Step 1 is incre-
mented from 00 to 03, by the HDC for each word transfer to get all
eight command bytes.
Block transfers are initiated as in Step 1 except that the third state
loaded is FE. The state DE was a single word transfer. The direction
of transfer is determined by data line DATA7 when initializing the
high order address lines. Status is read by the HDC at the end of
every block or word transfer, and at the start of every new com-
mand.
To complete a command status must be returned to the host. The
status information returned is that defined by the 'Request Sense'
command. To do this, 2 status words must be transferred to the
command block. The host DMA is setup for a word transfer, by set-
ting the LD2, LD1, and the LDO counters similar to the read of the
command block byte 12 (see Step 1). The four status bytes: ERROR
CODE, LUN:LADD2. LADD1. and LADDO are loaded into the FIFO on
the rising edge of PCSD-, a word at a time. As usual, the DMA status
is examined, between word transfers. If the command, just executed
by the HDC required a disk access, then the ADV (address valid) bit
is ¦set Otherwise ADV = 0 to indicate that the LSA, reported in the 4
byte status block, is meaningless. This completes the instruction.
The host is acknowledged by writing state BF to set the host
vectored interrupt line low. Also IREQ- is deasserted by the HDC.
In the 68000 memory located at an address determined by Amiga
DOS is a 16 byte command block. The first byte received through
the FIFO is the MSB even byte, followed by the LSB odd byte.
During the command block transfer phase, 8 bytes specifying the
command are read by the HDC. The command block is organized as
follows:
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