Commodore Amiga A500 Technical Reference Manual page 195

PIN PIN
NAME NUMBER
RGA8-RGA1 26 thru 33
HSY* 81
VSY* 79
CSY* 80
LP* 78
RST* 18
INT3* 17
DMAL 18
BLS* 19
28MHZ 34
XCLK 35
SIGNAL
DIRECTION DESCRIPTION
OUT Output bus. The 8 bit output bus allows the device
and the processor to access registers located outside
the device.
This line is bidirectional and buffered. This signal is
the horizontal synchronization pulse and is NTSC
compatible. When set as an input an external video
source drives this signal to synchronize the horizontal
beam counter.
This line is bidirectional and buffered. This signal is
the vertical synchronization pulse and is NTSC com-
patible. When set as an input, an external video
source drives this signal to synchronize the vertical
beam counter.
OUT This signal is the composite video synchronization
pulse and is NTSC compatible.
OUT Active low. This input is used to indicate when the
light pen is coincident with the monitor beam.
IN Active low. This input initializes the device to a
known state.
OUT Active low. The device asserts this line to indicate
that the blitter has completed the requested data
transfer and that the blitter is then ready to accept
another task.
IN Active high. When this signal is enabled, it indicates
that an external device is requesting audio and/or
disk DMA cycles to be executed by the device.
IN Active low. When this line is asserted, the device sus-
pends its blitter operation and allows the processer
to have control of the cycle.
IN This is a 28.63636MHz input clock that provides the
master time base for the device. This clock is enabled
only when XCLKEN* is high.
IN This input is an alternate master clock to the device.
It is enabled when XCLKEN* is low. This input is used
to synchronize the device with an external video
source.
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