Commodore Amiga A500 Technical Reference Manual page 174

Command Complete
Acknowledge (BF)
Word Transfer (DF)
Reset DMA (7F)
HOST/HDC COMMAND
PROTOCOL
Step 1: Setting Up The
DMA Address
Step 2: Reading Data
This will cause the assertion of the host vectored interrupt line to its
active low state to indicate the completion of a command by the
HDC.
This will set the internal DMA circuit into a single word tranfer. On
completion of the word transfer, the DMA resets to a block transfer
mode. Hence this state must be strobed for every word transfer de-
sired.
This state, followed by state TF\ resets the DMA circuits and clears
the FIFO. This state should be strobed on power-up and to clear any
FIFO underflow or overflow conditions.
Commands are passed to the HDC through the DMA circuit. When
the host requires a disk transfer a command block will be setup in
the 68000 memory followed by the host asserting the 1REQ- line
low. The Z80 will then go through a sequence for each IREQ as dis-
cussed below:
State FB is loaded into the DMA circuit with PCSS- followed by
PCSD- with the hex value of desired high ordered address. Bit 7 of
the data bus determines the direction of the transfer, a low will
cause a write operation to host and a high will cause a read from
host.
Then state FD is loaded into the DMA circuit with PCSS followed by
PCSD- with the value of desired address on the data bus. This sets
up address lines A16-A9.
State DE is loaded with PCSS- for a word transfer. A value of 06 is
loaded with PCSD- to point to the 12th and 13th bytes of the com-
mand block. On the falling edge of PCSD- the DMA word cycle will
begin. Byte 12 must be FF before the command is executed.
The state EF is loaded with PCSS- so that on the falling edge of
PCSD- internal DMA status will be outputed. The data lines DATA7,
DATA6, and DATA5 are examined until they are high indicating com-
pletion of the DMA cycle and that data has shifted through the FIFO.
For a block write operation to the disk,DATA6 is examined until low.
The HDC will sample the status for about 20 mS. until the data bus
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