Commodore Amiga A500 Technical Reference Manual page 224

REG NAME
C SDR S7
Interrupt Control (ICR)
READ (INT DATA)
REG NAME
D IRA IR
WRITE (INT MASK)
REG NAME
D IRC S/C
drain, with passive pullups, to allow such a common bus. Protocol
for slave/master selection can be transmitted over the serial bus. or
via dedicated handshaking lines.
S6 S5 S4
There are five sources of interrupts on the 8520: underflow from
TIMER A. underflow from TIMER B, TOD ALARM. Serial Port full/
empty and FLAG. A single register provides masking and interrupt
information. The Interrupt Control Register consists of a write-only
MASK register and a read-only DATA register. Any interrupt which is
enabled by the MASK register will set the IR bit (MSB) of the DATA
register and bring the IRQ pin low. In a multi-chip system, the IR bit
can be polled to detect which chip has generated an interrupt re-
quest.
The interrupt DATA register is cleared and the IRQ line returns high
following a read of the DATA register. Since each interrupt sets an
interrupt bit regardless of the MASK, and each interrupt bit can be
selectively masked to prevent the generation of a processor inter-
rupt, it is possible to intermix polled interrupts with true interrupts.
However, polling the IR bit will cause the DATA register to clear,
therefore, it is up to the user to preserve the information contained
in the DATA register if any polled interrupts were present.
The MASK register provides convenient control of individual mask
bits. When writing to the MASK register, if bit 7 (SET/CLEAR) of
the data written is a ZERO, any mask bit written with a one will be
cleared, while those mask bits written with a zero will be
unaffected. If bit 7 of the data written is a ONE, any mask bit
written with a one will be set. while those mask bits written with a
zero will be unaffected. In order for an interrupt flag to set IR and
generate an Interrupt Request, corresponding MASK bit must be
set.
0 0 FLG
X X FLG
S3 S2 S1
SP ALRM TB
SP ALRM TB
221
S0
TA
TA