Commodore Amiga A500 Technical Reference Manual page 173

FIFO Access (F7)
Read DMA Status (EF)
Reset IREQ- (9F)
This state opens a path to an internal FIFO that is 64 bytes in
length. The failing edge of PCSD- will start to shift data out of the
FIFO for a read or shift data into the FIFO on the rising edge of
PCSD- if the R/W- was set low with LD2. The DMA will initiate host
memory access, done a word at a time, whenever the FIFO is half
full. A typical memory access without any wait states takes 4 cycles,
each cycle being about 140 nS.
The host DMA status must be read before initiating any data trans-
fer, since its FIFO can be shared by another device. At the end of ev-
ery word or block transfer initiated by the hard disk controller, the
status must be read to ensure successful data transfer completion.
Status is not read after every word in a block transfer. After the last
byte, in a block transfer, has been strobed into the DMA controller
approximately 12 uS are needed to ensure that the DMA status lines
are all high. To read the status, any number of PCSD- strobes may
be used before initiating another DMA cycle. The DMA internal
status available after the falling edge of PCSD- is interpreted as
follows:
DATA BIT 7: This line will be high if no DMA was requested
or a DMA cycle was completed. After completion
of a word or a block transfer, this bit will be set
high. A low indicates DMA busy status.
DATA BIT 6: This bit is high if a byte of data is available to be
read from the FIFO, or if there is a byte to be
written and the FIFO is not full. At the end of a
block write operation to the disk, since there
are no more bytes available, this bit is set low.
DATA BIT 5: This line is low if the FIFO overflowed or
underflowed. This may occur during a disk
transfer if the DMA circuit does not receive a
bus acknowledge signal from another device on
the 68000 motherboard, before the FIFO
becomes full or empty. Under this condition the
FIFO is cleared by the Z80, before any other
data transfer can be initiated.
DATA BITS 4-0: These data lines will be logic zero.
This state will force IREQ- line to high impedance. It is set low by
the host
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