Commodore Amiga A500 Technical Reference Manual page 199

Figure 6.4 shows a typical DMA channel; almost all channels have
RAM as source and chip registers as destination.
R A M
SO U R C E
A D D R ESS
FIGURE 6.4. DMA CHANNEL (TYPICAL)
The pointer must be preloaded and is automatically incremented
each time a data transfer occurs.
Each controller utilizes one or more of these DMA channels for its
own purposes. The following is a brief summary of these controllers
and the DMA channels they use.
A-BLITTER (4 CHANNELS)
196
8370/ EX TER N A L
R EG I STER
16 BI T
D ATA BU S
D EST
M A
BU S
18 BI T
R EQ A D D R ESS
EN C O D ER
DMA CHANNEL CONTROLLER
The Blitter uses four DMA channels,
three sources and one destination as
previously described.
Once the Blitter has been started, the
four DMA channels are synchronized and
pipelined to automatically handle the data
transfers without further processor
intervention. The images are manipulated
in memory, independent of the display
(bitplane DMA).
R G A
A D D R ESS
BU S
8 BI T
R A M A D D R ESS
PO I N TER