Commodore Amiga A1000 Hardware Reference Manual

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AMIGA HARDWARE

REFERENCE MANUAL

Amiga 1200 PAL

Table of Contents

Summary of Contents for Commodore Amiga A1000

Page 2: Table Of Contents
AMIGA HARDWARE REFERENCE MANUAL TABLE OF CONTENTS Chapter 1 INTRODUCTION Components of the Amiga ........2 THE MC68000 AND THE AMIGA CUSTOM CHIPS....2 VCR AND DIRECT CAMERA INTERFACE......5 PERIPHERALS..........5 SYSTEM EXPANDABILITY AND ADAPTABILITY....6 About the Examples........7 Some Caveats to Hardware Level Programmers ....9 Chapter 2 COPROCESSOR HARDWARE ......13 Introduction..........13 ABOUT THIS CHAPTER........14...
Page 3 Bit-Plane Assignment in Dual-playfield Mode .....62 COLOR REGISTERS IN DUAL-PLAYFIELD MODE ....65 DUAL-PLAYFIELD PRIORITY AND CONTROL ....66 ACTIVATING DUAL-PLAYFIELD MODE .......67 DUAL PLAYFIELD SUMMARY .......67 Bit-planes and Display Windows of All Sizes .....68 WHEN THE BIG PICTURE IS LRGR THAN THE DISPLAY WINDOW .68 MAXIMUM DISPLAY WINDOW SIZE......74 Moving (Scrolling) Playfields ......75 VERTICAL SCROLLING........75...
Page 4 DECIDING WHICH CHANNEL TO USE......134 CREATING THE WAVEFORM DATA......134 TELLING THE SYSTEM ABOUT THE DATA ....136 SELECTING THE VOLUME ........136 SELECTING THE DATA OUTPUT RATE.......137 PLAYING THE WAVEFORM ........140 STOPPING THE AUDIO DMA.......141 SUMMARY..........142 EXAMPLE..........142 Producing Complex Sounds........143 JOINING TONES ........143 PLAYING MULTIPLE TONES AT THE SAME TIME....145 MODULATING SOUND ........145 Producing High-quality Sound......148...
Page 5 HOW COLLISIONS ARE DETERMINED......207 HOW TO INTERPRET THE COLLISION DATA ....208 HOW COLLISION DETECTION IS CONTROLLED ....209 Beam Position Detection.........210 USING THE BEAM POSITION COUNTER......210 Interrupts ..........211 NONMASKABLE INTERRUPT .......212 MASKABLE INTERRUPTS........212 USER INTERFACE TO THE INTERRUPT SYSTEM ....212 INTERRUPT CONTROL REGISTERS ......212 SETTING AND CLEARING BITS......213 DMA Control ..........217 Processor Access to Chip Memory......217...
Page 6 INPUT MODE ..........324 OUTPUT MODE .........324 BIDIRECTIONAL FEATURE .......325 Interrupt Control Register (ICR) .......325 READ INTERRUPT CONTROL REGISTER .....326 WRITE INTERRUPT CONTROL MASK ......326 Control Registers ........327 CONTROL REGISTER A ........327 BIT MAP OF REGISTER CRA ......328 BIT MAP OF REGISTER CRB ......329 Port Signal Assignments.........329 Hardware Connection Details......332 INTERFACE SIGNALS ........332...
Page 7 LIST OF FIGURES Figure 1-1 Block Diagram for the Amiga Computer Family....11 Figure 2-1 Interlaced Bit-Plane in RAM......30 Figure 3-1 How the Video Display Picture Is Produced....34 Figure 3-2 What Is a Pixel?........35 Figure 3-3 How Bit-planes Select a Color......37 Figure 3-4 Significance of Bit-Plane Data in Selecting Colors..38 Figure 3-5 Interlacing..........44 Figure 3-6 Effect of Interlaced Mode on Edges of Objects..44...
Page 8 Figure 6-9 DMA Time Slot Allocation ......190 Figure 6-10 Norma 68000 Cycle ........191 Figure 6-11 Time Slots Used by a Six Bit Plane Display ..192 Figure 6-12 Time Slots Used by a High Resolution Display ..192 Figure 6-13 Blitter Block Diagram .......194 Figure 7-1 Inter-Sprite Fixed Priorities ......202 Figure 7-2 Analogy for Video Priority ......203 Figure 7-3 Sprite playfield Priority ......206...
Page 9 LIST OF TABLES Table 2-1 Interrupting the 68000........31 Table 2-2 Copper Instruction Summary ......32 Table 3-1 Colors in a Single Playfield......39 Table 3-2 Portion of the Color Table ......40 Table 3-3 Contents of the Color Registers ......41 Table 3-4 Sample Color Register Contents ......41 Table 3-5 Setting the Number of Bit-Planes......42 Table 3-6 Lines in a Normal Playfield......43 Table 3-7 Playfield Memory Requirements, NTSC.....46...
Page 10: Chapter 1 Introduction
CHAPTER 1 INTRODUCTION The Amiga family of computers consists of several models, each of which has been designed on the same premise to provide the user with a low cost computer that features high cost performance. The Amiga does this through the use of custom silicon hardware that yields advanced graphics and sound features.
Page 11: Components Of The Amiga
COMPONENTS OF THE AMIGA These are the hardware components of the Amiga: o Motorola MC68000 16/32 bit main processor. The Amiga also supports the 68010, 68020, and 68030 processors as an option. o 512K bytes of internal RAM, expandable to 1 MB on the A500 and A2000. o 256K bytes of ROM containing a real time, multitasking operating system with sound, graphics, and animation support routines.
Page 12 In addition to the 68000, the Amiga contains special purpose hardware known as the "custom chips" that greatly enhance system performance. The term "custom chips" refers to the 3 integrated circuits which were designed specifically for the Amiga computer. These three custom chips (called Agnus, Paula, and Denise) each contain the logic to handle a specific set of tasks, such as video, sound, direct memory access (DMA), or graphics.
Page 13 Additionally, you can use system hardware to detect collisions between objects and have your program react to such collisions. o Custom bit blitter used for high speed data movement, adaptable to bitplane animation. The blitter has been designed to efficiently retrieve data from up to three sources, combine the data in one of 256 different possible ways, and optionally store the combined data in a destination area.
Page 14: Vcr And Direct Camera Interface
Another primary feature of the Amiga hardware is the ability to dynamically control which part of the chip memory is used for the background display. audio, and sprites. The Amiga is not limited to a small, specific area of RAM for a frame buffer. Instead, the system allows display bitplanes, sprite processor control lists, coprocessor instruction lists, or audio channel control lists to be located anywhere within chip memory.
Page 15: System Expandability And Adaptability
SYSTEM EXPANDABILITY AND ADAPTABILITY New peripheral devices may be easily added to all Amiga models. These devices are automatically recognized and used by system software through a well defined, well documented linking procedure called AUTOCONFIG. On the A500 and A1000 models, peripheral devices can be added to the Amiga's 86 pin expansion connector, including additional external RAM.
Page 16: About The Examples
ABOUT THE EXAMPLES The examples in this book all demonstrate direct manipulation of the Amiga hardware. However, as a general rule, it is not permissible to directly access the hardware in the Amiga unless your software either has full control of the system, or has arbitrated via the OS for exclusive access to the particular parts of the hardware you wish to control.
Page 17 NOTE The offset values of the registers are the addresses that the Copper must use to talk to the registers. For example, in assembler: INCLUDE "exec/types.i" INCLUDE "hardware/custom.i" XREF custom ; External reference Start: _custom,a0 ; Use a0 as base register move.w #$7FFF,intena(a0) ;...
Page 18: Some Caveats To Hardware Level Programmers
SOME CAVEATS TO HARDWARE LEVEL PROGRAMMERS The Amiga is available in a variety of models and configurations, and is further diversified by a wealth of add-on expansion peripherals and processor replacements. In addition, even standard Amiga hardware such as the keyboard and floppy disks, are supplied by a number of different manufacturers and may vary subtly in both their timing and in their ability to perform outside of their specified capabilities.
Page 19 Do not read, write, or use any currently undefined address ranges. The current and future usage of such areas is reserved by Commodore and is definitely subject to change. If you are using the system libraries, devices, and resources, you must follow the defined interface.
Page 20: Figure 1-1 Block Diagram For The Amiga Computer Family
Figure 1-1: Block Diagram for the Amiga Computer Family. - Introduction 11 -...
Page 21 - 12 Introduction -...
Page 22: Chapter 2 Coprocessor Hardware
Chapter 2 COPROCESSOR HARDWARE INTRODUCTION The Copper is a general purpose coprocessor that resides in one of the Amiga's custom chips. It retrieves is instructions via direct memory access (DMA). The Copper can control nearly the entire graphics system, freeing the 68000 to execute program logic; it can also directly affect the contents of most of the chip control registers.
Page 23: About This Chapter
One of the features of the Copper is its ability to WAIT for a specific video beam position, then MOVE data into a system register. During the WAIT period, the Copper examines the contents of the video beam position counter directly. This means that while the Copper is waiting for the beam to reach a specific position, it does not use the memory bus at all.
Page 24: The Move Instruction
All Copper instructions consist of two 16-bit words in sequential memory locations. Each time the Copper fetches an instruction, it fetches both words. The MOVE and SKIP instructions require two memory cycles and two instruction words. Because only the odd memory cycles are requested by the Copper, four memory cycle times are required per instruction.
Page 25 The Copper can store data into the following registers: o Any register whose address is $20 or above. o Any register whose address is between $10 and $20 if the Copper danger bit is a 1. The Copper danger bit is in the Copper's control register, COPCON, which is described in the "Control Register"...
Page 26: The Wait Instruction
THE WAIT INSTRUCTION The WAIT instruction causes the Copper to wait until the video beam counters are equal to (or greater than) the coordinates specified in the instruction. While waiting, the Copper is off the bus and not using memory cycles. The first instruction word contains the vertical and horizontal coordinates of the beam position.
Page 27: Horizontal Beam Position
comparison.) The line number will never be greater than $FF The horizontal position has a maximum value of $E2. This means that the largest number that will ever appear in the comparison is $FFE2. When waiting for $FFE2, the line $FF will be reached, but the horizontal position $FE will never happen.
Page 28: The Comparison Enable Bits
INSTRUCTION EXPLANATION [ ... other instructions ... ] WAIT for position (0,255) At this point, the vertical counter appears to wrap to 0 because the comparison works on the least significant bits of the vertical count. WAIT for any horizontal position with Thus the total of 256+6 = 262 vertical position 0 through 256, covering lines of video beam travel...
Page 29: Using The Copper Registers
USING THE COPPER REGISTERS There are several machine registers and strobe addresses dedicated to the Copper: o Location registers o Jump address strobes o Control register LOCATION REGISTERS The Copper has two sets of location registers: COP1LCH High 3 bits of first Copper list address. COP1LCL Low 16 bits of first Copper list address.
Page 30: Jump Strobe Address
NOTE At the start of each vertical blanking interval, COP1LC is automatically used to start the program counter. That is, no matter what the Copper is doing, when the end of vertical blanking occurs, the Copper is automatically forced to restart its operations at the address contained in COP1LC.
Page 31: Putting Together A Copper Instruction List
PUTTING TOGETHER A COPPER INSTRUCTION LIST The Copper instruction list contains all the register resetting done during the vertical blanking interval and the register modifications necessary for making mid-screen alterations. As you are planning what will happen during each display field, you may find it easier to think of each aspect of the display as a separate subsystem, such as playfields, sprites, audio, interrupts, and so on.
Page 32 As you create Copper instruction lists, note that the final list must be in the same order as that in which the video beam creates the display. The video beam traverses the screen from position (0,0) in the upper left hand corner of the screen to the end of the display (226,262) NTSC (or (226,312) PAL) in the lower right hand corner.
Page 33: Complete Sample Copper List
COMPLETE SAMPLE COPPER LIST The following example shows a complete Copper list. This list is for two bitplanes-one at $21000 and one at $25000. At the top of the screen, the color registers are loaded with the following values: REGISTER COLOR COLOR00 white...
Page 34: Loops And Branches
COPPERLIST: ; Set up pointers to two bit planes DC.W BPL1PTH,$0002 ;Move S0002 into register $0E0 (BPL1PTH) DC.W BPL1PTL,$1000 ;Move $1000 into register $0E2 (BPL1PTL) DC.W BPL2PTH,$0002 ;Move $0002 into register $0E4 (BPL2PTH) DC.W BPL2PTL,$5000 ;Move $5000 into register $0E6 (BPL2PTL) ;...
Page 35: Stopping The Copper
initialize a location register. It is assumed that the user has already created the correct Copper instruction list at location "mycoplist." ; Install the copper list CUSTOM,a1 ; a1 = address of custom chips MYCOPLIST(pc),a0 ; Address of our copper list MOVE.L a0,COP1LC(a1) ;...
Page 36: Advanced Topics
ADVANCED TOPICS THE SKIP INSTRUCTION The SKIP instruction causes the Copper to skip the next instruction if the video beam counters are equal to or greater than the value given in the instruction. The contents of the SKIP instructions words are shown below. They are identical to the WAIT instruction, except that bit 0 of the second instruction word is a 1 to identify this as a SKIP instruction.
Page 37: Copper Loops And Branches And Comparison Enable
The following example SKIP instruction skips the instruction following it if VP (vertical beam position) is greater than or equal to 100 ($64). DC.W $6401,$FF01 ; If VP >= 100, ; skip next instruction (ignore HP) COPPER LOOPS AND BRANCHES AND COMPARISON ENABLE You can change the value in the location registers at any time and use this value to construct loops in the instruction list.
Page 38 HOW IT WORKS: Both loops are, for the most part, exactly the same. In each, the Copper waits until the vertical position register has $?F (? is any hex digit) in it, at which point we issue a Copper interrupt to the Amiga hardware. To make sure that the Copper does not loop back before the vertical position has changed and cause another interrupt on the same scan line, wait for the horizontal position to be $E2 alter each interrupt.
Page 39: Using The Copper In Interlaced Mode
DC.W COPJMP2,$0 ; Force a jump to COP2LC ; Whatever cleanup copper code that might be needed here... ; Since there are 262 lines in NTSC, and we stopped at 255, there is a ; bit of time available DC.W $FFFF,$FFFE ;...
Page 40: Using The Copper With The Blitter
To get the Copper to execute the correct list, you set an interrupt to the 68000 just after the first line of the display. When the interrupt is executed, you change the contents of the COP1LC location register to point to the second list. Then, during the vertical blanking interval, COP1LC will be automatically reset to point to the original list.
Page 41: Summary Of Copper Instructions
SUMMARY OF COPPER INSTRUCTIONS The Table below shows a summary of the bit positions for each of the Copper instructions. See Appendix A for a summary of all registers. Table 2-2: Copper Instruction Summary Move Wait Skip Bit# RD15 RD14 RD13 RD12 RD11...
Page 42: Chapter 3 Playield Hardware
Chapter 3 PLAYFIELD HARDWARE INTRODUCTION The screen display consists of two basic parts, playfields, which are sometimes called backgrounds, and sprites, which are easily movable graphics objects. This chapter describes how to directly access hardware registers to form playfields. - Playfield Hardware 33 -...
Page 43: About This Chapter
This chapter begins with a brief overview of playfield features, including definitions of some fundamental terms, and continues with the following major topics: o Forming a single "basic" playfield, which is a playfield the same size as the display screen. This section includes concepts that are fundamental to forming any playfield. o Forming a dual-playfield display in which one playfield is superimposed upon another.
Page 44: Figure 3-2 What Is A Pixel
The video beam produces about 262 video lines from top to bottom, of which 200 normally are visible on the screen with an NTSC system. With a PAL system, the beam produces 312 lines, of which 256 are normally visible. Each complete set of lines (262/NTSC or 312/PAL) is called a display field.
Page 45 o In low-resolution mode, the normal playfield has a width of 320 pixels. o High-resolution mode gives finer horizontal resolution 640 pixels in the same physical display area. o In non-interlaced mode, the normal NTSC playfield has a height of 200 video lines. The normal mal PAL screen has a height of 256 video lines.
Page 46: Figure 3-3 How Bit-Planes Select A Color
_______________________________ Bit plane 5 ____________________________ |0 |_ -------- Bit plane 4 |_|0 |_ _________________________ |_|1 |_ \__ See below |_|1 |_ Bit plane 3 |_|1 | ______________________ |__| ----- Bit plane 2 ___________________ | |_| Bit plane 1 \-------------- One pixel Bits from planes 5,4,3,2,1 Color Registers _______________________...
Page 47: Forming A Basic Playfield
Sample data for 4 pixels Data in Bit-Plane 5 Most Significant Data in Bit-Plane 4 Data in Bit-Plane 3 Data in Bit-Plane 2 Data in Bit-Plane 1 Least Significant Value 6 COLOR 6 Value 11 COLOR 11 Value 18 COLOR 18 Value 28 COLOR 28 Figure 34: Significance of Bit-Plane Data in Selecting Colors You also have the choice of defining two separate playfields, each formed from up to three...
Page 48: Height And Width Of The Playfield
o Vertical resolution, or interlacing. o Data fetch and modulo, which tell the system how much data to put on a horizontal line and how to fetch data from memory to the screen. In addition, you need to allocate memory to store the playfield, set pointers to tell the system where to find the data in memory, and (optionally) write a Copper routine to handle redisplay of the playfield.
Page 49: Table 3-2 Portion Of The Color Table
THE COLOR TABLE The color Table contains 32 registers, and you may load a different color into each of the registers. Here is a condensed view of the contents of the color Table: Table 3-2: Portion of the Color Table Register Name Contents Meaning...
Page 50: Table 3-3 Contents Of The Color Registers
Table 3-3: Contents of the Color Registers Bits Bits 15 -12 Unused Bits 11 - 8 Red Bits 7 - 4 Green Bits 3 - 0 Blue Table 3-4 shows some sample color register bit assignments and the resulting colors. At the end of the chapter is a more extensive list.
Page 51: Table 3-5 Setting The Number Of Bit-Planes
You select the number of bit-planes by writing the number into the register BPLCON0 (for Bit Plane Control Register 0) The relevant bits are bits 14, 13, and 12, named BPU2, BPU1, and BPU0 (for "Bit Planes Used"). Table 3-5 shows the values to write to these bits and how the system assigns bit-plane numbers.
Page 52: Selecting Horizontal And Vertical Resolution
o Genlock audio is disabled. o Light pen is disabled. o Interlaced mode is disabled. o External resynchronization is disabled. (genlock) SELECTING HORIZONTAL AND VERTICAL RESOLUTION Standard home television screens are best suited for low-resolution displays. Low- resolution mode provides 320 pixels for each horizontal line. High-resolution monochrome and RGB monitors can produce displays in high-resolution mode, which provides 640 pixels for each horizontal line.
Page 53: Figure 3-5 Interlacing
line 1_________________________ | _________________________ |\ | _________________________ | \ _________ Field 1 __________________ _________ \ |___|______________|___Line 1 | _________________________ | >|___|______________|___ | _________________________ | Line 2 |___________________________| | Video display| (400 lines) | line 1_________________________ | _________________________ | |__\|/_____________| | _________________________ | _________ Field 2 (same physical space as used...
Page 54 To set interlaced or non-interlaced mode, you write to bit 2, LACE, in register BPLCON0: Interlaced mode write 1 to bit 2. Non-interlaced mode write 0 to bit 2. As explained above in "Setting the Number of Bit-Planes," bits in BPLCON0 are not independently set.
Page 55: Allocating Memory For Bit-Planes
ALLOCATING MEMORY FOR BIT-PLANES After you set the number of bit-planes and specify resolution modes, you are ready to allocate memory. A bit-plane consists of an end-to-end sequence of words at consecutive memory locations. When operating under the Amiga operating system, use a system call such as AllocMem() to remove a block of memory from the free list and make it available to the program.
Page 56: Table 3-8 Playfield Memory Requirements, Pal
Table 3-8: Playfield Memory Requirements, PAL Number of Bytes Picture Size Modes per Bit-Plane 320 X 256 Low-resolution, 8,192 non-interlaced 320 X 512 Low-resolution, 16,384 interlaced 640 X 256 High-resolution, 16,384 non-interlaced 640 X 512 High-resolution, 32,768 interlaced NTSC EXAMPLE OF BIT PLANE SIZE For example, using a normal, NTSC, low-resolution, non-interlaced display with 320 pixels across each display line and a total of 200 display lines, each line of the bit-plane requires 40 bytes (320 bits divided by 8 bits per byte = 40).
Page 57: Figure 3-7 Memory Organization For A Basic Bit-Plane
_____________ _____________ | | | | | | | | _____________________\ | | | | | | | | |_|_|_|_|_|_|_| |_|_|_|_|_|_|_| Mem. Location N Mem. location N+38 _____________ _____________ | | | | | | | | _____________________\ | | | | | | | | |_|_|_|_|_|_|_| |_|_|_|_|_|_|_| Mem.
Page 58: Coding The Bit-Planes For Correct Coloring
CODING THE BIT-PLANES FOR CORRECT COLORING After you have specified the number of bit-planes and set the bit-plane pointers, you can actually write the color register codes into the bit-planes. A ONE-OR TWO-COLOR PLAYFIELD For a one-color playfield, all you need do is write "0"s in all the bits of the single bit-plane as shown in the example below.
Page 59: Defining The Size Of The Display Window
Figure 3-8: Combining Bit-planes You place the correct "1"s and "0"s in both bit-planes to give each pixel in the picture above the correct color. In a single playfield you can combine up to five bit-planes in this way. Using five bit- planes allows a choice of 32 different colors for any single pixel.
Page 60: Figure 3-9 Positioning The On-Screen Display
playfield or scroll the playfield through the window. You can also define display windows larger than the basic playfield. These larger playfields and different-sized display windows are described in The section below called "Bit-Planes and Display Windows of All Sizes." You determine the size of the display window by specifying the vertical and horizontal positions at which the window starts and stops and writing these positions to the display window registers.
Page 61 SETTING THE DISPLAY WINDOW STARTING POSITION A horizontal starting position of approximately $81 and a vertical starting position of approximately $2C centers the display on most standard television screens. If you select high-resolution mode (640 pixels horizontally) or interlaced mode (400 lines NTSC, 512 PAL) the starting position does not change.
Page 62: Telling The System How To Fetch And Display Data
The following example sets DIWSTOP for a basic playfield to $F4 for the vertical position and $C1 for the horizontal position. CUSTOM,a0 ; Get base address of custom hardware... MOVE.W #$F4C1,DIWSTOP(a0) ; Display window stop register... Table 3-9: DIWSTRT AND DIWSTOP Summary. -Nominal Values- -Possible Values- NTSC...
Page 63: Figure 3-10 Data Fetched For The First Line When Modulo=0
The relationship between data-fetch start and stop is; DDFSTRT = DDFSTOP-(8*(word count-1))for low resolution DDFSTRT = DDFSTOP-(4*(word count-2))for high resolution The normal low-resolution DDFSTOP is ($00D0). The normal high-resolution DDFSTOP is ($00D4) The following example sets data-fetch start to $0038 and data-fetch stop to $00D0 for a basic playfield.
Page 64: Figure 3-11 Data Fetched For The Second Line When Modulo=0
After the first line is fetched, the bit-plane pointers BPLxPTH and BPLxPTL contain the value START+40. The modulo (in this case, 0) is added to the current value of the pointer, so when the pointer begins the data fetch for the next line, it fetches the data you want on that line.
Page 65: Displaying And Redisplaying The Playfield
The bit-planes for a full-screen-sized, interlaced display are 400 NTSC (512 PAL), rather than 200 NTSC (256 PAL), lines long. Assuming that the playfield in memory is the normal 320 pixels wide, data for the interlaced picture begins at the following locations (these are all byte addresses): Line 1 START Line 2 START+40...
Page 66: Basic Playfield Summary
BASIC PLAYFIELD SUMMARY The steps for defining a basic playfield are summarized below: 1. Define Playfield Characteristics a. Specify height in lines: o For NTSC: * 200 for non-interlaced mode. * 400 for interlaced mode. o For PAL: * 256 for non-interlaced mode. * 512 for interlaced mode.
Page 67 d. Specify resolution: o Low resolution: * 320 pixels in each horizontal line. * Clear bit 15 in register BPLCON0 (HIRES). o High resolution: * 640 pixels in each horizontal line. * Set bit 15 in register BPLCON0 (HIRES). e. Specify interlaced or non-interlaced mode: o Interlaced mode: * 400 vertical lines for NTSC, 512 for PAL.
Page 68: Examples Of Forming Basic Playfields
4. Define Data Fetch. Set registers DDFSTRT and DDFSTOP: o For DDFSTRT, use the horizontal position as shown in "Setting the Display Window Starting Position." o For DDFSTOP, use the horizontal position as shown in "Setting the Display Window Stopping Position." 5.
Page 69 CLOOP: MOVE.L (a2),(a1)+ ; Move a word CMPI.L #$FFFFFFFE,(a2)+ ; Check for last longword of Copper list CLOOP ; Loop until entire copper list i9 moved ; Point Copper at Copper list MOVE.L #$20000,COP1LCH(a0) ; Write to Copper location register MOVE.W COPJMP1(a0),d0 ;...
Page 70 ; Start DMA MOVE.W #(DMAF_SETCLR!DMAF_RASTER!DMAF_MASTER),DMACON(a0) ; Enable bit-plane DMA only, no Copper ; Because this example has no Copper list, it sits in a ; loop waiting for the vertical blanking interval. When it ; comes, you check the LOF ( long frame bit in VPOSR.
Page 71: Forming A Dual-Playfield Display
FORMING A DUAL-PLAYFIELD DISPLAY For more flexibility in designing your background display, you can specify two playfields instead of one. In dual-playfield mode, one playfield is displayed directly in front of the other. For example, a computer game display might have some action going on in one playfield in the back-ground, while the other playfield is showing a control panel in the foreground.
Page 72: Figure 3-12 A Dual-Playfield Display
Figure 3-12: A dual Playfield display. - Playfield Hardware 63 -...
Page 73: Figure 3-13 How Bit-Planes Are Assigned To Dual Playfields
Number of Bitplanes "turned on" Playfield 1* Playfield 2* None None __________ |__________| __________ __________ |__________| |__________| __________ __________ |1 ________|_ |_|3 |__________| |__________| __________ __________ |1 ________|_ |2 ________|_ |_|3 |_|4 |__________| |__________| __________ __________ |1 ________|_ |2 ________|_ |_|3 ________|_ |_|4 |_|5...
Page 74: Color Registers In Dual-Playfield Mode
COLOR REGISTERS IN DUAL-PLAYFIELD MODE When you are using dual playfields, the hardware interprets color numbers for playfield 1 from the bit combinations of bit-planes 1, 3, and 5. Bits from PLANE 5 have the highest significance and form the most significant digit of the color register number. Bits from PLANE O have the lowest significance.
Page 75: Dual-Playfield Priority And Control
Combination 000 selects transparent mode, to show the color of whatever object (the other playfield, a sprite, or the background color) may be "behind" the playfield. Table 3-12 shows the color registers for high-resolution, dual-playfield mode. Table 3-12: Playfields 1 and 2 Color Registers- High-resolution Mode PLAYFIELD 1 Color Combination...
Page 76: Activating Dual-Playfield Mode
NOTE You must take special care when scrolling one playfield and holding the other stationary. When you are scrolling low-resolution playfields, you must fetch one word more than the width of the playfield you are trying to scroll (two words more in high-resolution mode) in order to provide some data to display, when the actual scrolling takes place.
Page 77: Bit-Planes And Display Windows Of All Sizes
BIT-PLANES AND DISPLAY WINDOWS OF ALL SIZES You have seen how to form single and dual playfields in which the playfield in memory is the same size as the display window. This section shows you how to define and use a playfield whose big picture in memory is larger than the display window, how to define display windows that are larger or smaller than the normal playfield size, and how to move the display window in the big picture.
Page 78: Figure 3-14 Memory Picture Larger Than The Display
START START+78 ------------------------------------------------- Width of the Bit-Plane Defined in RAM | Width of defined | screen on which | bit-plane data is | to appear ------------------------------------------------- Figure 3-14: Memory Picture Larger than the Display Because 40 bytes are to be fetched for each line, the data fetch for line 1 is as shown in Figure 3-15.
Page 79: Figure 3-16 Data Fetch For The Second Line When Modulo=40
Data for Line 2: Location: START+80 START+82 START+84... START+118 Leftmost Next Word Next Word Last Display Display Word Word Figure 3-16: Data Fetch for the Second Line When Modulo = 40 To display the right half of the big picture, you set up a vertical blanking routine to start the bit-plane pointers at location START+40 rather than START with the modulo remaining at 40.
Page 80 SPECIFYING THE DATA FETCH The data-fetch registers specify the beginning and end positions for data placement on each horizontal line of the display. You specify data fetch in the same way as shown in the section called "Forming a Basic Playfield." MEMORY ALLOCATION For larger memory pictures, you need to allocate more memory.
Page 81: Figure 3-19 Display Window Horizontal Starting Position
FULL SCREEN AREA --------------------------------------------- HSTART of DISPLAY | WINDOW occurs in this region. --------------------------------------------- Figure 3-19: Display Window Horizontal Starting Position The eight bits allocated to VSTART are assigned to the first 256 positions counting down from the top of the display. FULL SCREEN AREA --------------------------------------------- 0 Vstart of display window |...
Page 82: Figure 3-21 Display Window Horizontal Stopping Position
SELECTING THE STOPPING POSITION The stopping position for the display window is the horizontal and vertical coordinates of the lower right-hand corner of the display window. One register, DIWSTOP, contains both coordinates, known as HSTOP and VSTOP. See the notes in the "Forming a Basic Playfield" section for instructions on setting these registers.
Page 83: Maximum Display Window Size
FULL SCREEN AREA --------------------------------------------- 0 _________________________________|___128 Vstop of display window occurs in the region. | (NTSC)______|___262 --------------------------------------------- Figure 3-22: Display Window Vertical Stopping Position To set the display window stopping position, write HSTOP into bits 0 through 7 and VSTOP into bits 8 through 15 of DIWSTOP.
Page 84: Moving (Scrolling) Playfields
because the rightmost limit remains ($D8) and only one word is fetched at this limit. However, horizontal blanking actually limits the displayable video to 368 low-resolution pixels (23 words). These numbers are the same both for NTSC and for PAL. In addition, it should be noted that using a data-fetch start earlier than ($38) will disable some sprites.
Page 85: Figure 3-23 Vertical Scrolling
is shown and the picture scrolls downward. On an NTSC system, with a display that has 200 vertical lines, each step can be as little as 1/200th of the screen. In interlaced mode each step could be 1/400th of the screen if clever manipulation of the pointers is used, but it is recommended that scrolling be done two lines at a time to maintain the odd/even field relationship.
Page 86: Horizontal Scrolling
HORIZONTAL SCROLLING You can scroll playfields horizontally from left to right or right to left on the screen. You control the speed of scrolling by specifying the amount of delay in pixels. Delay means that an extra word of data is fetched but not immediately displayed. The extra word is placed just to the left of the window's leftmost edge and before normal data fetch.
Page 87: Figure 3-24 Horizontal Scrolling
Figure 3-24: Horizontal Scrolling - 78 playfield hardware -...
Page 88: Figure 3-25 Memory Picture Larger Than The Display Window
START START+38 START+78 ______________________________________________ Display window width | <--------- Memory Picture Width -----------> | |______________________|_______________________| Figure 3-25: Memory Picture Larger Than the Display Window Data for Line 1: Location: START START+2 START+4... START+40 Leftmost Next Word Next Word Last Display display word word Figure 3-26: Data for Line 1 - Horizontal Scrolling...
Page 89: Scrolled Playfield Summary
SPECIFYING AMOUNT OF DELAY The amount of delay in horizontal scrolling is controlled by bits 7-0 in BPLCON1. You set the delay separately for each playfield; bits 3-0 for playfield 1 (bit-planes 1, 3, and 5) and bits 7-4 for playfield 2 (bit-planes 2, 4, and 6). NOTE Always set all six bits, even if you have only one playfield.
Page 90: Advanced Topics
ADVANCED TOPICS This section describes features that are used less often or are optional. INTERACTIONS AMONG PLAYFIELDS AND OTHER OBJECTS Playfields share the display with sprites. Chapter 7, "System Control Hardware," shows how playfields can be given different video display priorities relative to the sprites and how playfields can collide with (overlap) the sprites or each other.
Page 91 o If the 6-5 bit combination is 10, the color of the pixel immediately to the left of this pixel is duplicated and then modified. The bit-combinations from planes 4 -1 are used to replace the four "red" bits. o If the 6-5 bit combination is 11, the color of the pixel immediately to the left of this pixel is duplicated and then modified.
Page 92 MOVE.W #2000,d0 ; 2000 longwords per bit-plane MOVE.L #$21000,a1 ; Point a1 at bit-plane 1 MOVE.L #$23000,a2 ; Point a2 at bit-plane 2 MOVE.L #$25000,a3 ; Point a3 at bit-plane 3 MOVE.L #$27000,a4 ; Point a4 at bit-plane 4 MOVE.L #$29000,a5 ;...
Page 93: Forming A Display With Several Different Playfeld
FORMING A DISPLAY WITH SEVERAL DIFFERENT PLAYFIELDS The graphics library provides the ability to split the screen into several "ViewPorts", each with its own colors and resolutions. See the Amiga ROM Kernel Manual for more information. USING AN EXTERNAL VIDEO SOURCE An optional board that provides genlock is available for the Amiga.
Page 94 Bit 8 - GAUD (genlock audio enable) 1 = Genlock audio enabled 0 = Genlock audio disabled (in blanking periods, this bit goes out on the pixel switch Bit 9 - COLOR ON (color enable) 1 = composite video color-burst enabled 0 = composite video color-burst disabled Bit 10 - DBLPF (double-playfield enable) 1 = dual playfields enabled...
Page 95 BPLCON2 - Bit-plane Control Bit 6 - PF2PRI 1 = Playfield 2 has priority 0 = Playfield 1 has priority Bits 0-5 Playfield sprite priority Bits 7-15 not used DDFSTRT - Data-fetch Start (Beginning position for data fetch) Bits 15-8 - not used Bits 7-2 - pixel position H8-H3 Bits...
Page 96: Summary Of Color Selection
DIWSTOP - Display Window Stop (Ending vertical and horizontal coordinates) Bits 15-8 - VSTOP (V7-V0) Bits 7-0 - HSTOP (H7-H0) BPL1MOD - Bit-plane Modulo (Odd-numbered bit-planes, playfield 1) BPL2MOD - Bit-plane Modulo (Even-numbered bit-planes, playfield 2) SUMMARY OF COLOR SELECTION This section contains summaries of playfield color selection including color register contents, example colors, and the differences in color selection in high-resolution and low- resolution modes.
Page 97: Some Sample Color Register Contents
SOME SAMPLE COLOR REGISTER CONTENTS Table 3-16 shows a variety of colors and the hexadecimal values to load into the color registers for these colors. Table 3-16: Some Register Values and Resulting Colors Value Color Value Color $FFF White $1FB Light aqua $D00 Brick red...
Page 98: Table 3-17 Low-Resolution Color Selection
Table 3-17: Low-resolution Color Selection Singe Playfield Dual Playfields Normal Mode Hold-and-modify Mode Color Register (Bit-planes 5,4,3,2,1) (Bit-planes 4,3,2,1) Number Playfield 1 Bit-planes 5,3,1 00000 0000 00001 0001 00010 0010 00011 0011 00100 0100 00101 0101 00110 0100 00111 0111 Playfield 2 Bit-planes 6,4,2 01000...
Page 99: Color Selection In Hold-And-Modify Mode
COLOR SELECTION IN HOLD-AND-MODIFY MODE In hold-and-modify mode, the color register contents are changed as shown in Table 3- 18. This mode is in effect only if bit 10 of BPLCON0 = 1. Table 3-18: Color Selection in Hold-and-modify Mode Bitplane 6 Bitplane 5 Result...
Page 100: Table 3-19 High-Resolution Color Selection
Table 3-19 High-resolution Color Selection Single Dual Color Playfield Playfields Register Bit-planes 4,3,2,1 Number Playfield 1 Bit-planes 3,1 0000 00 * 0 ** 0001 0010 0011 0100 0101 NOT USED 0110 IN THIS MODE 0111 Playfield 2 Bit-planes 4.2 1000 00 * 1001 1010...
Page 101 - 92 Playfield Hardware -...
Page 102: Chapter 4 Sprite Hardware
CHAPTER 4 SPRITE HARDWARE INTRODUCTION Sprites are hardware objects that are created and moved independently of the playfield display and independently of each other. Together with playfields, sprites form the graphics display of the Amiga. You can create more complex animation effects by using the blitter, which is described in the chapter called "Blitter Hardware."...
Page 103: About This Chapter
Sprite DMA channels can be reused several times within the same display field. Thus, you are not limited to having only eight sprites on the screen at the same time. ABOUT THIS CHAPTER This chapter discusses the following topics: o Defining the size, shape, color, and screen position of sprites. o Displaying and moving sprites.
Page 104: Figure 4-1 Defining Sprite On-Screen Position
(0,0) Visible screen area \_______________________ ____________|____________/ |______ |-------X--------| |__\/__| Figure 4-1: (Defining Sprite On-screen Position) The amount of viewable area is also affected by the size of the playfield display window (defined by the values in DDFSTRT, DDFSTOP, DIWSTRT, DIWSTOP, etc.). See the "Playfield Hardware"...
Page 105: Figure 4-2 Position Of Sprites
Thus, 158 becomes the X value, which will be written into the data structure. NOTE The X position represents the location of the very first (leftmost) pixel in the full 16-bit- wide sprite. This is always the case, even if the leftmost pixels are specified as transparent and do not appear on the screen.
Page 106: Size Of Sprites
CLIPPED SPRITES As noted above, sprites will be partially or totally clipped if they pass across or beyond the boundaries of the display window. The values of 64 (horizontal) and 44 (vertical) are "normal" for a centred display on a standard NTSC video monitor. See Chapter 3, "Playfield Hardware", for more information on display offsets.
Page 107: Sprite Color
o o o o x x o o o o o o o o o o o o x x x x x x o o o o o o o o x x x x x x x x x x o o o o o o x x x x x x x x x x o o o o o o o o x x x x x x o o o o o o o o o o o o x x o o o o o o o o o o...
Page 108: Figure 4-5 Sprite Color Definition
Figure 4-5: (Sprite Color Definition) The 0s and 1s in the two data words that define each line of a sprite in the data structure form a binary number. This binary number points to one of the four color registers assigned to that particular sprite DMA channel.
Page 109: Figure 4-6 Color Register Assignments
Codes 01,10,or 11 select one of three possible registers from the normal color register from the normal color register group, from which the actual color data is taken. COLOR REGISTER SET _________________________ Unused | 16 00 |_________________________| Sprite 0 or 1 | 01 |_________________________| 10 |_________________________| |__ 11 |_________________________|...
Page 110: Designing A Sprite
DESIGNING A SPRITE For design purposes, it is convenient to lay out the sprite on paper first. You can show the desired colors as numbers from 0 to 3. For example, the spaceship shown above might look like this: 0000122332210000 0001223333221000 0012223333222100 0001223333221000...
Page 111: Table 4-1 Sprite Data Structure
Table 4-1: Sprite Data Structure Memory Location 16-bit Word Function Sprite control word 1 Vertical and horizontal start position Sprite control word 2 Vertical stop position Color descriptor low word Color bits for line 1 Color descriptor high word Color bits for line 1 Color descriptor low word Color bits for line 2 Color descriptor high word...
Page 112: Figure 4-7 Data Structure Layout
Figure 4-7 PART ONE: (Data Structure Layout) Figure 4-7 PART TWO: (Data Structure Layout) <------------- 16 Bits -----------> _________________________________----\ _ Each group of words defines one vertical VSTART, HSTART usage of a sprite. |_________________________________| Contains starting location & physical VSTOP, control bits appearance of this |_________________________________| sprite image.
Page 113 SPRITE CONTROL WORD 1: SPRxPOS This word contains the vertical (VSTART) and horizontal (HSTART) starting position for the sprite. This is where the topmost line of the sprite will be positioned. Bits 15-8 contain the low 8 bits of VSTART Bits 7-0 contain the high 8 bits of HSTART SPRITE CONTROL WORD 2: SPRxCTL...
Page 114: Table 4-2 Sprite Color Registers
To form the color descriptor words, you first need to form a picture of the sprite, showing the color of each pixel as a number from 0 - 3. Each number represents one of the colors in the sprite's color registers. For example, here is the spaceship sprite again: 0000122332210000 0001223333221000 0012223333222100...
Page 115: Displaying A Sprite
hardware in the same manner as the original words that were first loaded into the control registers. If the VSTART value contained in these words is lower than the current beam position, this sprite will not be reused in this display field. For consistency, the value 0 should be used for both words when ending the usage of a sprite.
Page 116: Selecting A Dma Channel And Setting The Pointers
SELECTING A DMA CHANNEL AND SETTING THE POINTERS In deciding which DMA channel to use, you should take into consideration the colors assigned to the sprite and the sprite's video priority. The sprite DMA channel uses two pointers to read in sprite data and control words. During the vertical blanking interval before the first display of the sprite, you need to write the sprite's memory address into these pointers.
Page 117: Sprite Display Example
SPRITE DISPLAY EXAMPLE This example displays the spaceship sprite at location V = 65, H = 128. Remember to include the file "hw_examples.i", located in Appendix J. ; First, we set up a single bit-plane. LEA CUSTOM,a0 ; Point a0 at custom chips MOVE.W #$1200,BPLCON0(a0) ;...
Page 118 MOVE.L #$20000,COP1LC(a0) ; Fill bit-plane with $FFFFFFFF. MOVE.L #$21000,a1 ; Point A1 at bit-plane MOVE.W #l999,d0 ; 2000-1(for dbf) long words = 8000 bytes FLOOP MOVE.L #$FFFFFFFF,(al)+ ; Move a long word of $FFFFFFFF d0,FLOOP ; Decrement, repeat until false. ;...
Page 119: Moving A Sprite
MOVING A SPRITE A sprite generated in automatic mode can be moved by specifying a different position in the data structure. For each display field, the data is reread and the sprite redrawn. Therefore, if you change the position data before the sprite is redrawn, it will appear in a new position and will seem to be moving.
Page 120: Creating Additional Sprites
MOVE.W INTREQR(a0),d6 ; Read interrupt request word AND.W #$0020,d6 ; Mask off all but vertical blank bit VLOOP ; Loop until bit is a 1 MOVE.W #$0020,INTREQ(a0) ; Vertical bit is on, so reset it ;Please note that this will only work if you have turned OFF the Vertical ;blanking interrupt enable (not recommended for long periods).
Page 121: Sprite Priority
Table 4-3: Color Registers for Sprite Pairs SPRITE NUMBERS COLOUR REGISTERS 0 and 1 17-19 2 and 3 21-23 4 and 5 25-27 6 and 7 29-31 NOTE Some sprites become unusable when additional DMA cycles are allocated to displaying the screen, e.g.
Page 122: Reusing Sprite Dma Channels
REUSING SPRITE DMA CHANNELS Each of the eight sprite DMA channels can produce more than one independently controllable image. There may be times when you want more than eight objects, or you may be left with fewer than eight objects because you have attached some of the sprites to produce more colors or larger objects or overlapped some to produce more complex images.
Page 123: Figure 4-10 Typical Data Structure For Sprite Re-Use
SPRITE DISPLAY LIST ------\ _ Data describing ________________________________ the 1st vertical Increasing |________________________________| usage of this |________________________________| sprite. memory ________________________________ addresses |________________________________| |________________________________| _________ _________ _________ ________________________________ |________________________________| |________________________________| -----/ -----\ _ Data describing ________________________________ the 2nd vertical |________________________________| usage of this |________________________________| sprite.
Page 124: Overlapped Sprites
The following example displays the spaceship sprite and then redisplays it as a different object. Only the sprite data list is affected, so only the data list is shown here. However, the sprite looks best with the color registers set as shown in the xample.
Page 125: Figure 4-11 Overlapping Sprites (Not Attached)
Figure 4-11: overlapping Sprites (Not attached) You can create a wider sprite display by placing two sprites next to each other. instance, Figure 4-12 shows the spaceship sprite and how it can be made twice as large by using two sprites placed next to each other. - 116 Sprite Hardware -...
Page 126: Attached Sprites
(128,65) o_____________________ _| | |______|________|_____| (128,65) (144,65) o_____________________o_____________________ |_________|___________|__________|__________| Sprite 0 Sprite 1 Figure 4-12: Placing Sprites Next to Each Other ATTACHED SPRITES You can create sprites that have fifteen possible color choices (plus transparent) instead of three (plus transparent), by "attaching" two sprites. To create attached sprites, you must: o Use two channels per sprite, creating two sprites of the same size and located at the same position.
Page 127: Table 4-4 Data Words For First Line Of Spaceship Sprite
Sprites can be attached in the following combinations: Sprite 1 to sprite 0 Sprite 3 to sprite 2 Sprite 5 to sprite 4 Sprite 7 to sprite 6 Any or all of these attachments can be active during the same displayfield. As an example, assume that you wish to have more colors in the spaceship sprite and you are using sprite DMA channels 0 and 1.
Page 128: Table 4-5 Color Registers In Attached Sprites
The binary numbers 0 through 15 select registers 17 through 31 as shown in Table 4-5. Table 4-5: Color Registers in Attached Sprites Decimal Binary ColorRegister Number Number Number 0000 16 * 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011...
Page 129: Manual Mode
The following data structure is for the six-color spaceship made with two attached sprites. SPRITE0: DC.W $6D60,$7200 ;VSTART = 65, HSTART = 128 DC.W $0C30,$0000 ;First color descriptor word DC.W $1818,$0420 DC.W $342C,$0E70 DC.W $1818,$0420 DC.W $0C30,$0000 DC.W $0000,$0000 ;End of sprite 0 SPRITE1: DC.W $6D60,$7280...
Page 130: Sprite Hardware Details
SPRITE HARDWARE DETAILS Sprites are produced by the circuitry shown in Figure 4-13. This Figure shows in block form how a pair of data words becomes a set of pixels displayed on the screen. The circuitry elements for sprite display are explained below. o Sprite data registers.
Page 131: Figure 4-13 Sprite Control Circuitry
_________________ Beam counter | |(Horizontal pos.)| ____________________ |_________________| |SPRxDATA load decode| (68000 or DMA) ________\/_______ |____________________| | Equal Compensator |______ ___________________ |_________________| |SPRxPOS load decode| | ________|______| (68000 or DMA) _______/__\____|_ |___________________| | | SPRxPOS (Horiz.)| |_________________| <-"ARM SPRITE"-> ________|____________________________o ____________/ |___ _______...
Page 132 o Writing to the sprite A data register enables the horizontal comparator. This enables output to the screen when the horizontal position of the video beam equals the horizontal value in the position register. o If the comparator is enabled, the sprite data will be sent to the display, with the leftmost pixel of the sprite data placed at the position defined in the horizontal part of SPRxPOS.
Page 133: Summary Of Sprite Registers
SUMMARY OF SPRITE REGISTERS There are eight complete sets of registers used to describe the sprites. Each set consists of five registers. Only the registers for sprite O are described here. All of the others are the same, except for the name of the register, which includes the appropriate number. POINTERS Pointers are registers that are used by the system to point to the current data being used.
Page 134 NOTE The sprites have a placement resolution on a full screen of 320 by 200 NTSC (320 by 256 PAL). The sprite resolution is independent of the bit-plane resolution. BIT POSITIONS: o Bits 15-8 specify the vertical start position, bits V7 - V0. o Bits 7-0 specify the horizontal start position, bits H8 - H1.
Page 135: Data Registers
Position and control registers for the other sprites are: SPR1POS SPR1CTL SPR2POS SPR2CTL SPR3POS SPR3CTL SPR4POS SPR4CTL SPR5POS SPRSCTL SPR6POS SPR6CTL SPR7POS SPR7CTL DATA REGISTERS The following registers, although defined in the address space of the main processor, are normally used only by the display processor. They are the holding registers for the data obtained by DMA cycles.
Page 136: Table 4-6 Color Registers For Single Sprites
Table 4-6: Color Registers for Single Sprites SINGLE SPRITES COLOR Sprite Value Register 0 or 1 Not used * 2 or 3 Not used * 4 or 5 Not used * 6 or 7 Not used * * Selects transparent mode. If the bit combinations from attached sprites are as shown in Table 4-7, then the colors will be taken from the registers shown.
Page 137: Interactions Among Sprites And Other Objects
Table 4-7: Color Registers for Attached Sprites ATTACHED SPRITES Color Value Register 0000 Selects transparent mode 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 INTERACTIONS AMONG SPRITES AND OTHER OBJECTS Playfields share the display with sprites. Chapter 7, "System Control Hardware," shows how playfields can be given different video display priorities relative to the sprites and how playfields can collide with (overlap) the sprites or each other.
Page 138: Chapter 5 Audio Hardware
CHAPTER 5 AUDIO HARDWARE INTRODUCTION This chapter shows you how to directly access the audio hardware to produce sounds. The major topics in this chapter are: o A brief overview of how a computer produces sound. o How to produce simple steady and changing sounds and more complex ones. - Audio Hardware 129 -...
Page 139: Introducing Sound Generation
o How to use the audio channels for special effects, wiring them for stereo sound if desired, or using one channel to modulate another. o How to produce quality sound within the system limitations. A section at the end of the chapter gives you values to use for creating musical notes on the equal-tempered musical scale.
Page 140: Figure 5-1 Sine Waveform
Figure 5-1: Sine waveform In electronic sound recording and output devices, the attributes of sounds are represented by the parameters of amplitude and frequency. Frequency is the number of cycles per second, and the most common unit of frequency is the Hertz (Hz), which is 1 cycle per second.
Page 141 The third attribute of a sound, timbre, depends on the presence or absence of overtones, or harmonics. Any complex waveform is actually a mixture of sine waves of different amplitudes, frequencies, and phases (the starting point of the waveform on the time axis).
Page 142: The Amiga Sound Hardware
Figure 5-2: Digitized Amplitude Values DIGITISED AMPLITUDE VALUES TIME SINE SQUARE TRIANGLE -100 -100 -100 -103 -100 -121 -100 -127 -100 -100 -121 -100 -103 -100 -100 -100 THE AMIGA SOUND HARDWARE The Amiga has four hardware sound channels. You can independently program each of the channels to produce complex sound effects.
Page 143: Forming And Playing A Sound
Each audio channel includes an eight-bit digital-to-analog converter driven by a direct memory access (DMA) channel. The audio DMA can retrieve two data samples during each horizontal video scan line. For simple, steady tones, the DMA can automatically play a waveform repeatedly;...
Page 144: Table 5-1 Sample Audio Data Set For Channel 0
Sound data is organized as a set of eight-bit data items; each item is a sample from the waveform. Each data word retrieved for the audio channel consists of two samples. Sample values can range from -128 to +127. As an example, the data set shown below produces a close approximation to a sine wave. NOTE The data is stored in byte address order with the first digitized amplitude value at the lowest byte address, the second at the next byte address, and so on.
Page 145: Telling The System About The Data
TELLING THE SYSTEM ABOUT THE DATA In order to retrieve the sound data for the audio channel, the system needs to know where the data is located and how long (in words) the data is. The location registers AUDxLCH and AUDxLCL contain the high three bits and the low fifteen bits, respectively, of the starting address of the audio data.
Page 146: Selecting The Data Output Rate
For a typical output at volume 64, with maximum data values of -128 to 127, the voltage output is between +.4 volts and -.4 volts. Some volume levels and the corresponding decibel values are shown in Table 5-2. Table 5-2: Volume Values VOLUME DECIBEL VALUE...
Page 147 LIMITATIONS ON SELECTION OF SAMPLING PERIOD The sampling period is limited by the number of DMA cycles allocated to an audio channel. Each audio channel is allocated one DMA slot per horizontal scan line of the screen display. An audio channel can retrieve two data samples during each horizontal scan line. The following calculation gives the maximum sampling rate in samples per second.
Page 148: Figure 5-3 Example Sine Wave
NOTE The Clock Interval is derived from the clock constant, where: clock interval = -------------- clock constant then scale the result to microseconds. In all of these calculations "ticks" and "timing intervals" refer to the same thing. SPECIFYING THE PERIOD VALUE After you have selected the desired interval between data samples, you can calculate the value to place in the period register by using the period formula: desired interval...
Page 149: Playing The Waveform
Sampled Values: -127 To output the series of eight samples at 1 KHz (1,000 cycles per second), each full cycle is output in 1/1000th of a second. Therefore, each individual value must be retrieved in 1/8th of that time. This translates to 1,000 microseconds per waveform or 125 microseconds per sample.
Page 150: Stopping The Audio Dma
Table 5-3: DMA and Audio Channel Enable Bits DMACON REGISTER Name Function SET/CLR When this bit is written as a 1, it sets any bit in DMACONW for which the corresponding bit position is also a 1, leaving all other bits alone. DMAEN Only while this bit is a 1 can any direct memory access occur.
Page 151: Summary
SUMMARY These are the steps necessary to produce a steady tone: 1. Define the waveform. 2. Create the data set containing the pairs of data samples (data words). Normally, a data set contains the definition of one waveform. 3. Set the location registers: AUDxLCH (high three bits) AUDxLCL (low fifteen bits) 4.
Page 152: Producing Complex Sounds
SETAUDOVOLUME: MOVE.W #64,AUD0VOL(a0) ;Use maximum volume SETAUDOPERIOD: MOVE.W #447,AUD0PER(a0) BEGINCHAN0: MOVE.W #(DMAF_SETCLR!DMAF_AUD0!DMAF_MASTER),DMACON(a0) ; Return to main code DS.W 0 ; Be sure word-aligned SINEDATA: DC.B 0, 90, 127, 90, 0, -90, -127, -90 PRODUCING COMPLEX SOUNDS In addition to simple tones, you can create more complex sounds, such as different musical notes joined into a one-voice melody, different notes played at the same time, or modulated sounds.
Page 153 EXAMPLE This example details the system audio DMA action in a step-by-step fashion. Suppose you wanted to join together a sine and a triangle waveform, end-to-end, for a special audio effect, alternating between them. The following sequence shows the action of your program as well as its interaction with the audio DMA system.
Page 154: Playing Multiple Tones At The Same Time
SYSTEM RESPONSE As soon as DMA starts, a. Copy to "back-up" length register from AUDOLEN. b. Copy to "back-up'' location register from AUDOLCL (will be used as a pointer showing current data word to fetch). c. Create an interrupt for the 68000 saying that it has completed retrieving working copies of length and location registers.
Page 155: Table 5-4 Data Interpretation In Attach Mode
To modulate only the amplitude of the audio output, you must attach a channel as a volume modulator. Define the modulator channel's data set as a series of words, each containing volume information in the following format: BITS FUNCTION 15 - 7 Not used 6 - 0 Volume information, V6-V0...
Page 156: Table 5-5 Channel Attachment For Modulation
The lengths of the data sets of the modulator and the modulated channels are completely independent. Channels are attached by the system in a predetermined order, as shown in Table 5-5. To attach a channel as a modulator, you set its attach bit to 1. If you set either the volume or period attach bits for a channel, that channel's audio output will be disabled;...
Page 157: Producing High-Quality Sound
PRODUCING HIGH-QUALITY SOUND When trying to create high-quality sound, you need to consider the following factors: o Waveform transitions. o Sampling rate. o Efficiency. o Noise reduction. o Avoidance of aliasing distortion. o Limitations of the low pass filter. MAKING WAVEFORM TRANSITIONS To avoid unpleasant sounds when you change from one waveform to another, you need to make the transitions smooth.
Page 158: Efficiency
Figure 5.4: Waveform with Multiple Cycles EFFICIENCY A certain amount of overhead is involved in the handling of audio DMA. If you are trying to produce a smooth continuous audio synthesis, you should try to avoid as much of the system control overhead as possible.
Page 159: Noise Reduction
NOISE REDUCTION To reduce noise levels and produce an accurate sound, try to use the full range of -128 to 127 when you represent a waveform. This reduces how much noise (quantization error) will be added to the signal by using more bits of precision. Quantization noise is caused by the introduction of round-off error.
Page 160: Figure 5-5 Frequency Domain Plot Of Low-Pass Filter
0 db |____ Filter response -30 db |_______\_________________________________\ Filter passes all frequencies below about 5KHz Figure 5-5: Frequency Domain Plot of Low-Pass Filter Figure 5-6 shows that it is permissible to use a 12 KHz sampling rate to produce a 4 KHz waveform.
Page 161: Low-Pass Filter
^ Filter response 10 KHz sampling frequency 0 db |____ \Diff. | 4| \ | -30 db |____|__\|__|____|______________________\ / 05 Desired output frequency Figure 5-7: Some Aliasing Distortion All of this gives rise to the following equation, showing that the sampling frequency must exceed the output frequency by at least 7 KHz, so that the beat frequency will be above the cut-off range of the anti-aliasing filter: Minimum sampling rate = highest frequency component + 7 KHz...
Page 162: Using Direct (Non-Dma) Audio Output
Table 5-6: Sampling Rate and Frequency Relationship Sampling Sampling Maximum Output Period Rate (KHz) Frequency (KHz) Maximum sampling rate Minimum sampling rate for 7 KHz output Sampling rate too low for 7 KHz output In A2000s with 2 layer motherboards and later AS00 models there is a control bit that allows the audio output to bypass the low pass filter.
Page 163: The Equal-Tempered Musical Scale
THE EQUAL-TEMPERED MUSICAL SCALE Table 5-7 gives a close approximation of the equal-tempered scale over one octave when the sample size is 16 bytes. The "Period" column gives the period count you enter into the period register. The length register AUDxLEN should be set to 8 (16 bytes = 8 words). The sample should represent one cycle of the waveform.
Page 164 A sample for an equal-tempered scale typically represents one full cycle of a note. To avoid aliasing distortion with these samples you should use period values in the range 124-256 only. Periods from 124-256 correspond to playback rates in the range 14-28K samples per second which makes the most effective use of the Amiga's 7 kHz cut-off filter to prevent noise.
Page 165: Table 5-8 Five Octave Even-Tempered Scale
Table 5-8: Five Octave Even-tempered Scale NTSC Ideal Actual NTSC Actual PAL Period Period Note Frequency Frequency Frequency 55.00 55.05 54.98 58.27 58.26 58.21 61.73 61.87 61.85 65.40 65.34 65.35 69.29 69.22 69.27 73.41 73.59 73.30 77.78 77.68 77.83 82.40 82.25 82.47 87.30...
Page 166 NTSC Ideal Actual NTSC Actual PAL Period Period Note Frequency Frequency Frequency 440.0 440.4 439.8 466.16 466.09 465.72 493.88 494.96 494.82 523.25 522.71 522.83 554.37 553.77 554.20 587.33 588.74 586.46 622.25 621.45 622.70 659.26 658.00 659.76 698.46 699.13 697.11 739.99 740.80 738.94 783.99...
Page 167 256 BYTE SAMPLE -98 -100 -102 -104 -106 -108 -110 -112 -114 -116 -118 -120 -122 -124 -126 -127 -126 -124 -122 -120 -118 -116 -114 -112 -110 -108 -106 -104 -102 -100 128 BYTE SAMPLE 124 -127 -124 -120 -116 -112 -108 -104 -100 64 BYTE SAMPLE -96 -104 -112 -120 -127 -120 -112 -104 32 BYTE SAMPLE...
Page 168: Decibel Values For Volume Ranges
DECIBEL VALUES FOR VOLUME RANGES Table 5-9 provides the corresponding decibel values for the volume ranges of the Amiga system. Table 5-9: Decibel Values and Volume Ranges Volume Decibel Value Volume Decibel Value -6.0 -0.1 -6.3 -0.3 -6.6 -0.4 -6.9 -0.6 -7.2 -0.7...
Page 169: The Audio State Machine
THE AUDIO STATE MACHINE For an explanation of the various states, refer to Figure 5-8. There is one audio state machine for each channel. The machine has eight states and is clocked at the clock constant rate (3.58 MHz NTSC). Three of the states are basically unused and just transfer back to the idle (000) state.
Page 170 AUDxON DMA on "x" indicates channel number (signal from DMACON). AUDxIP Audio interrupt pending (input to channel from interrupt circuitry). AUDxIR Audio interrupt request (output from channel to interrupt circuitry) intreq1 Interrupt request that combines with intreq2 to form AUDxIR intreq2 Prepare for interrupt request.
Page 171: Figure 5-8 Audio State Diagram
napnav /AUDxAV * /AUDxAP + AUDxAV - no attach stuff or else attach volume. Condition for normal DMA and interrupt requests. sq2,1,0 The name of the state flip-flops, MSB to LSB. Figure 5-8: Audio State Diagram - 162 Audio Hardware -...
Page 172: Chapter 6 Blitter Hardware
Chapter 6 BLITTER HARDWARE INTRODUCTION The blitter is one of the two co-processors in the Amiga. Part of the Agnus chip, it is used to copy rectangular blocks of memory around and to draw lines. When copying memory, it is approximately twice as fast as the 68000, able to move almost four megabytes per second.
Page 173: Memory Layout
The blitter can only access CHIP memory - that portion of memory accessible by the display hardware. Attempting to use the blitter to read or write FAST or other non-CHIP memory may result in destruction of the contents of CHIP memory. A "blit"...
Page 174: Figure 6-1 How Images Are Stored In Memory
Each of the DMA channels can be independently enabled or disabled. The enable bits are bits SRCA, SRCB, SRCC, and DEST in control register zero (BLTCON0). When disabled, no memory cycles will be executed for that channel and, for a source channel, the constant value stored in the data register of that channel will be used for each blitter cycle.
Page 175 that is given in words. The height is stored in the upper ten bits of the BLTSIZE register, with zero representing a height of 1024 rows. Thus, the largest blit possible with the current Amiga blitter is 1024 by 1024 pixels. However, shifting and masking operations may require an extra word be fetched for each raster scan line, making the maximum practical horizontal width 1008 pixels.
Page 176: Figure 6-2 Bltxp And Bltxmod Calculations
Figure 6-2: BLTxPTR and BLTxMOD calculations NOTE The blitter can be used to process linear rather than rectangular regions by setting the horizontal or vertical count in BLTSIZE to 1. Because each DMA channel has its own modulo register, data can be moved among bitplanes of different widths.
Page 177: Function Generator
FUNCTION GENERATOR The blitter can combine the data from the three source DMA channels in up to 256 different ways to generate the values stored by the destination DMA channel. These sources might be one bitplane from each of three separate graphics images. While each of these sources is a rectangular region composed of many points, the same logic operation will be performed on each point throughout the rectangular region.
Page 178: Designing The Lf Control Byte With Minterms
For another example, an LF control byte of $80 ( = 1000 0000 binary) turns on bits only for those points of the D destination rectangle where the corresponding bits of A, B, and C sources were all on (ABC = 1, bit 7 of LF on). All other points in the rectangle, which correspond to other combinations for A, B, and C, will be 0.
Page 179 "mask" that contains bits set wherever the car image is not transparent. This mask can be visualized as the shadow of the car from a light source at the same position as the viewer. NOTE The mask for the car need only be a single bitplane regardless of the depth of the background bitplane.
Page 180: Table 6-1 Table Of Common Minterm Values
Table 6-1: Table of Common Minterm Values Selected BLTCON0 Selected BLTCON0 Equation LF Code Equation LF Code D = A D = AB D = A D = AB D = B D = AB D = B D = AB D = C D = BC D = C...
Page 181: Designing The Lf Control Byte With Venn Diagrams
DESIGNING THE LF CONTROL BYTE WITH VENN DIAGRAMS Another way to arrive at a particular function is through the use of Venn diagrams: Figure 6-3: Blitter Minterm Venn Diagram 1. To select a function D=A (that is, destination = A source only), select only the minterms that are totally enclosed by the A-circle in the Figure above.
Page 182: Shifts And Masks
3. To use a function that is the inverse, or "not", of one of the sources, such as A, take all of the minterms not enclosed by the circle represented by A on the above Figure. In this case, we have minterms 0, 1, 2, and 3. Minterm Numbers 7 6 5 4 3 2 1 0 Selected Minterms 0 0 0 0 1 1 1 1...
Page 183 with zeros shifted in from the left. The second word will be the second word fetched from the A, shifted right, with the least significant (rightmost) four bits of the first word shifted in. Next, we will write the first word of the second row fetched from A, shifted four bits, with the least significant four bits of the last word from the first row shifted in.
Page 184: Figure 6-4 Extracting A Range Of Columns
|______________2 word source bitmap____________| |___Extract a 23-bit image_____| |_____16 bit word______| |______________________|_______|_______________| Source | 00000000 00000000 00000000 00000000 | DMA B | 11111111 11111111 11111111 11111111 | | 10101010 01010101 10101010 01010101 | |______________________________________________| ____V___________V_____ ___V___________V_____ Mask on | 11111111 11111111 | |11111110 00000000 | DMA A...
Page 185: Descending Mode
NOTE Even though the A channel is disabled, we use it in our logic function and preload the data register. Disabling a channel simply turns off the memory fetches for that channel; all other operations are still performed, only from a constant value stored in the channel's data register An alternative but more subtle way of accomplishing the same thing is to use an A shift of five, a first word mask of all ones, and a last word mask with the rightmost nine bits set...
Page 186: Copying Arbitrary Regions
COPYING ARBITRARY REGIONS One of the most common uses of the blitter is to move arbitrary rectangles of data from one bitplane to another, or to different positions within a bitplane. These rectangles are usually on arbitrary bit coordinates, so shifting and masking are necessary. There are further complications.
Page 187: Area Fill Mode
6. If the source and destination span the same number of words, use the A channel to mask either the source, as in 4, or the destination, as in 5. NOTE Conditions 2 and 3 can be contradictory if, for instance, you are trying to move an image one pixel down and to the right.
Page 188: Figure 6-5 Use Of The Fci Bit - Bit Is A 0
There is another bit (FILL_CARRYIN or bit 3 in BLTCON1) that forces the area "outside" the lines be filled; for the above example, with inclusive fill, the output would be; 11100111-11111111 with exclusive fill, the output would be; 11100011-11110111 BEFORE AFTER ____________________ ___________________...
Page 189: Blitter Done Flag
BEFORE AFTER EXCLUSIVE FILL ____________________ ___________________ 1111 1111 1111 1111 |____________________| |___________________| Figure 6-7: Single-Point Vertex Example The blitter uses the fill carry-in bit as the starting fin state beginning at the right most edge of each line. For each "1" bit in the source area, the blitter flips the fill state, either filling or not filling the space with ones.
Page 190: Multitasking And The Blitter
The solution is to read a chip memory or hardware register address with the processor before testing the bit. This can easily be done with the sequence: btst.b #DMAB_BLTDONE-8,DMACONR(a1) btst.b #DMAB_BLTDONE-8,DMACONR(a1) where a1 has been preloaded with the address of the hardware registers. The first "test" of the blitter done bit may not return the correct result, but the second blit.
Page 191: Zero Flag
ZERO FLAG A blitter zero flag is provided that can be tested to determine if the logic operation selected has resulted in zero bits for all destination bits, even if those destination bits are not written due to the D DMA channel being disabled. This feature is often useful for collision detection, by performing a logical "and"...
Page 192: Table 6-2 Typical Blitter Cycle Sequence
Bus cycles are dynamically allocated based on blitter operating mode; competing bus activity from processor, bitplanes, and other DMA channels; and other factors. Commodore Amiga does not guarantee the accuracy of or future adherence to this chart. We reserve the right to make product improvements or design changes in this area without notice.
Page 193: Line Mode
LINE MODE In addition to all of the functions described above, the blitter can draw patterned lines. The line draw mode is selected by setting bit 0 (LINEMODE) of BLTCON1, which changes the meaning of some other bits in BLTCON0 and BLTCON1. In line draw mode, the blitter can draw lines up to 1024 pixels long, it can draw them in a variety of modes, with a variety of textures, and can even draw them in a special way for simple area fill.
Page 194: Table 6-3 Bltcon1 Code Bits For Octant Line Drawing
Table 6-3: BLTCON1 Code Bits for Octant Line Drawing BLTCON1 Code Bits Octant # 0 1 1 1 1 1 1 0 1 0 1 0 0 0 0 1 0 0 We initialize BLTCON1 bits 4 through 2 according to the above Table. Now, we introduce the variables dx and dy, and set them to the absolute values of the difference between the x coordinates and the y coordinates of the endpoints of the line, respectively.
Page 195: Register Summary For Line Mode
The C and D pointer registers should be initialized to the word containing the first pixel of the line; the C and D modulo registers should be set to the width of the bitplane in bytes. The SRCA, SRCC, and DEST bits of BLTCON0 should be set to one, and the SRCB flag should be set to zero.
Page 196 BLTCON0 bits 15-12 = x1 modulo 15 BLTCON0 bits SRCA, SRCC, and SRCD = 1 BLTCON0 bit SRCB = 0 if exclusive-or line mode: then BLTCON0 LF control byte = ABC + AC else BLTCON0 LF control byte = AB + AC BLTCON1 bit LINEMODE = 1 BLTCON1 bit OVFLAG = 0 BLTCON1 bits 4-2 = octant number from Table...
Page 197: Blitter Speed
BLITTER SPEED The speed of the blitter depends entirely on which DMA channels are enabled. You might be using a DMA channel as a constant, but unless it is enabled, it does not count against you. The minimum blitter cycle is four ticks; the maximum is eight ticks. Use of the A register is always free.
Page 198: Blitter Operations And System Dma
BLITTER OPERATIONS AND SYSTEM DMA The operations of the blitter affect the performance of the rest of the system. the following sections explain how system performance is affected by blitter direct memory access priority, DMA time slot allocation, bus sharing between the 68000 and the display hardware, the operations of the blitter and Copper, and different playfield display sizes.
Page 199: Figure 6-9 Dma Time Slot Allocation
Figure 6-9: DMA time slot allocation. - 190 Blitter hardware -...
Page 200: Figure 6-10 Norma 68000 Cycle
The 68000 uses only the even-numbered memory access cycles. The 68000 spends about half of a complete processor instruction time doing internal operations and the other half accessing memory. Therefore, the allocation of alternate memory cycles to the 68000 makes it appear to the 68000 that it has the memory all of the time, and it will run at full speed.
Page 201: Figure 6-11 Time Slots Used By A Six Bit Plane Display
-TIMING CYCLE- --------------------------------- | 4 | 6 | 2 | | 3 | 5 | 1 | --------------------------------- Figure 6-11: Time Slots Used by a Six Bit Plane Display If you specify four high-resolution bit-planes (640 pixels wide), bit-plane DMA needs all of the available memory time slots during the display time just to fetch the 40 data words for each line of the four bit-planes (40 4 = 160 time slots).
Page 202: Blitter Block Diagram
As mentioned above, the blitter normally has a higher priority than the processor for DMA cycles. There are certain cases, however, when the blitter and the 68000 can share memory cycles. If given the chance, the blitter would steal every available memory cycle. Display, disk, and audio DMA take precedence over the blitter, so it cannot block them from bus access.
Page 203: Figure 6-13 Blitter Block Diagram
Figure 6-13: Blitter Block Diagram - 194 Blitter Hardware -...
Page 204: Blitter Key Points
BLITTER KEY POINTS This is a list of some key points that should be remembered when programming the blitter. o Write BLTSIZE last; writing this register starts the blit. o Modulos and pointers are in bytes; width is in words and height is in pixels. The least significant bit of all pointers and modules is ignored.
Page 205 ; of the blits is finished, the pointer in the blitter is pointing ; to the next word to be blitted. ; When this routine returns, the last blit is started and might ; not be finished, so be sure to call waitblit above before ;...
Page 206: Example: Simpleline
EXAMPLE: SimpleLine ; This example uses the line draw mode of the blitter ; to draw a line. The line is drawn with no pattern ; and a simple 'or' blit into a single bitplane. ; Input: d0=x1 dl=y1 d2=x2 d3=y2 d4=width a0=aptr include 'exec/types.i' include 'hardware/custom.i' include 'hardware/blit.i'...
Page 207 xyneg: neg.w ; y was negative, in one of [5,6] cmp.w d3,d2 ; is y>x? xynygtx ; if so, octant is 6 moveq.l #OCTANT5+LINEMODE,d5 ; otherwise, octant is 5 lineagain xynygtx: d2,d3 ; X must be greater than Y moveq.l #OCTANT6+LINEMODE,d5 ; we are in octant 6 lineagain: mulu.w d9,d1...
Page 208: Example: Rotatebits
EXAMPLE: RotateBits ; here we rotate bits. This code takes a single raster row of a ; bitplane, and 'rotates' it into an array of 16-bit words, setting ; the specified bit of each word in the array according to the ;...
Page 209 inloop ; Go into the loop again: move.w (a0)+,d3 ; Grab another word btst d2,(a3) ; Check blit done wait2: btst d2,(a3) ; Check again wait2 ; oops, not ready, loop around inloop: move.w d3,(a4) ; stuff new word to make vertical move.w d1,(a5) ;...
Page 210: Chapter 7 System Control Hardware
CHAPTER 7 SYSTEM CONTROL HARDWARE INTRODUCTION This chapter covers the control hardware of the Amiga system, including the following topics: o How playfield priorities may be specified relative to the sprites o How collisions between objects are sensed - System Control Hardware 201 -...
Page 211: Video Priorities
o How system direct memory access (DMA) is controlled o How interrupts are controlled and sensed o How reset and early powerup are controlled VIDEO PRIORITIES You can control the priorities of various objects on the screen to give the illusion of three dimensions.
Page 212: How Sprites Are Grouped
HOW SPRITES ARE GROUPED For playfield priority and collision purposes only, sprites are treated as four groups of two sprites each. The groups of sprites are: Sprites 0 and 1 Sprites 2 and 3 Sprites 4 and 5 Sprites 6 and 7 UNDERSTANDING VIDEO PRIORITIES The concept of video priorities is easy to understand if you imagine that four fingers of one of your hands represent the four pairs of sprites and two fingers of your other hand...
Page 213: Setting The Priority Control Register
Five possible positions can be chosen for each of the two "playfield fingers." For example, you can place playfield 1 on top of sprites 0 and 1 (0), between sprites O and 1 and sprites 2 and 3 (1), between sprites 2 and 3 and sprites 4 and 5 (2), between sprites 4 and 5 and sprites 6 and 7 (3), or beneath sprites 6 and 7 (4).
Page 214 Table 7-2: Priority of Playfields Based on Values of Bits PF1P2-PF1P0 Value Placement (from most important to least important) SP01 SP23 SP45 SP67 SP01 SP23 SP45 SP67 SP01 SP23 SP45 SP67 SP01 SP23 SP45 SP67 SP01 SP23 SP45 SP67 In this Table, PF1 stands for playfield 1, and SP01 stands for the group of sprites numbered 0 and 1.
Page 215: Figure 7-3 Sprite Playfield Priority
Figure 7-3: Sprite/Playfield Priority When everything is displayed together, sprite 0 is more important than playfield 2 but less important 3883 than playfield 1. So even though you can't see the boundary, the sprite disappears "behind" the invisible PF1 boundary. - 206 System Control Hardware -...
Page 216: Collision Detection
COLLISION DETECTION You can use the hardware to detect collisions between one sprite group and another sprite group, any sprite group and either of the playfields, the two playfields, or any combination of these items. The first kind of collision is typically used in a game operation to determine if a missile has collided with a moving player.
Page 217: How To Interpret The Collision Data
HOW TO INTERPRET THE COLLISION DATA The collision data register, CLXDAT, is read-only, and its contents are automatically cleared to 0 after it is read. Its bits are as shown in Table 7-3. Table 7-3: CLXDAT Bits Number Collisions Registered not used Sprite 4 (or 5) to sprite 6 (or 7) Sprite 2 (or 3) to sprite 6 (or 7)
Page 218: How Collision Detection Is Controlled
HOW COLLISION DETECTION IS CONTROLLED The collision control register, CLXCON, contains the bits that define certain characteristics of collision detection. Its bits are shown in Table 7-4. Table 7-4: CLXCON Bits Number Name Function ENSP7 Enable sprite 7 (OR with sprite 6) ENSPS Enable sprite 5 (OR with sprite 4) ENSP3...
Page 219: Beam Position Detection
BEAM POSITION DETECTION Sometimes you might want to synchronize the 68000 processor to the video beam that is creating the screen display. In some cases, you may also wish to update a part of the display memory after the system has already accessed the data from the memory for the display area.
Page 220: Interrupts
Table 7-5: Contents of the Beam Position Counter VPOSR Read-only Read the high bit of the vertical position (V8) and the frame-type bit. Bit 15 LOF (Long-framebit). Used to initialize interlaced displays. Bits 14-1 Unused Bit 0 High bit of the vertical position (V8).
Page 221: Nonmaskable Interrupt
NONMASKABLE INTERRUPT Interrupt level 7 is the non-maskable interrupt and is not generated anywhere in the current system. The raw interrupt lines of the 68000, IPL2 through IPL0, are brought out to the expansion connector and can be used to generate this level 7 interrupt for debugging purposes.
Page 222: Setting And Clearing Bits
INTREQ Interrupt request (status) - write only. Used by the processor to force a certain kind of interrupt to be processed (software interrupt). Also used to clear interrupt request flags once the interrupt process is completed. INIEQR Interrupt request (status) read - read only. Contains the bits that define which items are requesting interrupt service.
Page 223 MASTER INTERRUPT ENABLE Bit 14 of the interrupt registers (INTEN) is for interrupt enable. This is the master interrupt enable bit. If this bit is a 0, it disables all other interrupts. You may wish to clear this bit to temporarily disable all interrupts to do some critical processing task. NOTE This bit is used for enable/disable only.
Page 224 COPPER INTERRUPT Bit 4, COPER, is used by the Copper to issue a level 3 interrupt. The Copper can change the content of any of the bits of this register, as it can write any value into most of the machine registers.
Page 225: Figure 7-4 Interrupt Priorities
Bit 1, DSKBLK, indicates "disk block finished." It is used to indicate that the specified disk DMA task that you have requested has been completed. This bit generates a level 1 interrupt. More information about disk data transfer and interrupts may be found in Chapter 8, "Interface Hardware."...
Page 226: Dma Control
DMA CONTROL Many different direct memory access (DMA) functions occur during system operation. There is a read address as well as a write address to the DMA register so you can tell which DMA channels are enabled. The address names for the DMA register are as follows: DMACONR - Direct Memory Access Control - read-only.
Page 227: Table 7-6 Contents Of Dma Register
Table 7-6: Contents of DMA Register Number Name Function SET/CLR The set/reset control bit. See description of bit 15 under "Interrupts" above. BBUSY Blitter busy status - read-only BZERO Blitter zero status-read-only. Remains 1 if, during a blitter operation, the blitter output was always zero.
Page 228: Reset And Early Startup Operation
RESET AND EARLY STARTUP OPERATION When the Amiga is turned on or externally reset, the memory map is in a special state. An additional copy of the system ROM responds starting at memory location $00000000. The system RAM that would normally be located at this address is not available. On some Amiga models, portions of the RAM still respond.
Page 229 - 220 System Control Hardware -...
Page 230: Chapter 8 Interface Hardware
CHAPTER 8 INTERFACE HARDWARE INTRODUCTION This chapter covers the interface hardware through which the Amiga talks to the outside world, including the following features: o Two multiple purpose mouse/joystick/light pen control ports o Disk controller (for floppy disk drives & other MFM and GCR devices) - Interface Hardware 221 -...
Page 231: Controller Port Interface
o Keyboard o Centronics compatible parallel I/O interface (for printers) o RS232-C compatible serial interface (for external modems or other serial devices) o Video output connectors (RGB, monochrome, Nl SC, RF modulator, video slot) CONTROLLER PORT INTERFACE Each Amiga has two nine-pin connectors that can be used for input or output with many different kinds of controllers.
Page 232: Registers Used With The Controller Port
Table 8-1: Typical Controller Connections Mouse, Trackball, Proportional Driving Controller Proportional Joystick Controller (Pair) Joystick LightPen Forward V-pulse Button 3** Back H-pulse Left VQ-pulse Leftbutton Button 1 Right HQ-pulse Right button Button 2 Middle button** Right POT POT X Pen pressed to screen Button 1 Left button...
Page 233: Figure 8-2 Mouse Quadrature
READING MOUSE/TRACKBALL CONTROLLERS Pulses entering the mouse inputs are converted to separate horizontal and vertical counts. The 8 bit wide horizontal and vertical counter registers can track mouse movement without processor intervention. The mouse uses quadrature inputs. For each direction, a mechanical wheel inside the mouse will produce two pulse trains, one 90 degrees out of phase with the other (see Figure 8-2 for details).
Page 234 READING THE COUNTERS The mouse/trackball counter contents can be accessed by reading register addresses named JOY0DAT and JOY1DAT. These contains counts for ports 1 and 2 respectively. The contents of each of these 16-bit registers are as follows: Bits 15-8 Mouse/trackball vertical count Bits 7-0 Mouse/trackball horizontal count COUNTER LIMITATIONS These counters will "wrap around"...
Page 235: Table 8-2 Determining The Direction Of The Mouse
Table 8-2: Determining the Direction of the Mouse Previous Current Direction Count Count Up (Left) Down (Right) Down * Up ** NOTES FOR Table 8-1: * Because 200-45 = 155, which is more than 127, the true count must be 255 - ( 200-45) = 100;...
Page 236: Figure 8-3 Joystick To Counter Connections
Digital joystick switches are of the normally open type. When the switches are pressed, the input line is shorted to ground. An open switch reads as "1", a closed switch as "0". Reading the joystick input data logic states is not so simple, however, because the data registers for the joysticks are the same as the counters that are used for the mouse or trackball controllers.
Page 237: Table 8-3 Interpreting Data From Joy0Dat And Joy1Dat
Table 8-3: Interpreting Data from JOY0DAT and JOY1DAT Data Bit Interpretation True logic state of "right" switch. True logic state of "left" switch. 1 (XOR) 0 You must calculate the exclusive-or of bits 1 and 0 to obtain the logic state of the "back" switch. 9 (XOR) 8 You must calculate the exclusive-or of bits 9 and 8 to obtain the logic state of the "forward"...
Page 238: Figure 8-4 Typical Paddle Wiring Diagram
LEFT PADDLE RIGHT PADDLE resistive element resistive element ________ _______ ________ _______ \/\/\/\/ \/\/\/\/ | +5 | +5 |__________ |__________ Pin 7 Pin 9 Pin 7 Pin 5 |<-----Fire Button----->| |<-----Fire Button----->| Pin 8 Pin 3 Pin 8 Pin 4 Figure 8-4: Typical Paddle Wiring Diagram In an X-Y proportional joystick, the resistive elements are connected individually to the X and Y axes of a single controller stick.
Page 239: Figure 8-5 Effects Of Resistance On Charging Rate
Figure 8-5: Effects of Resistance on Charging Rate You normally issue POTGO at the beginning of a video screen, then read the values in the POT registers during the next vertical blanking period, just before issuing POTGO again. Nothing in the system prevents the counters from overflowing (wrapping past a count of 255).
Page 240: Figure 8-6 Potentiometer Charging Circuit
POTENTIOMETER SPECIFICATIONS The resistance of the potentiometers should be a linear taper. Based on the design of the integrating analog-to-digital converter used, the maximum resistance should be no more than 528K (470K +/- 10 percent is suggested) for either the X or Y pots. This is based on a charge capacitor of 0.047uf, +/- 10 percent, and a maximum time of 16.6 milliseconds for charge to full value, i.e.
Page 241 READING A LIGHT PEN A light pen can be connected to one of the controller ports. On the A1000, the light pen must be connected to port 1. Changing ports requires a minor internal modification. On the A500 and A2000 the default is port 2. An internal jumper can select port 1. Regardless of the port used, the light pen design is the same.
Page 242 READING THE LIGHT PEN REGISTERS The light pen register is at the same address as the beam counters. The bits are as follows: VPOSR: Bit 15 Long frame/short frame. 0=short frame Bits 14-1 Chip ID code. Do not depend on value! Bit 0 V8 (most significant bit of vertical position) VHPOSR:...
Page 243: Table 8-4 Potgo ($Dff034) And Potinp ($Dff016) Registers
A somewhat simplified method of determining the truth of the light pen value involves instructing the system software to read the register only during the internal vertical blanking period of 0<V20: 1. Read (long) VPOSR once, during the period of 0<V20. 2.
Page 244: Floppy Disk Controller
DOS) 5.25", IBM PC (MS-DOS) 3.5" and most CP/:/ITM formatted disks. The controller has provisions for reading and writing most disk using the Group Coded Recording (GCR) method, including Apple II disks. With motor speed tricks, the controller can read and write Commodore 1541/1571 format diskettes. - Interface Hardware 235 -...
Page 245: Registers Used By The Disk Subsystem
REGISTERS USED BY THE DISK SUBSYSTEM The disk subsystem uses two ports on the system's 8520 CIA chips, and several registers in the Paula chip: CIAAPRA ($BFE001) four input bits for disk sensing CIABPRB ($BFD100) eight output bits for disk selection, control and stepping ADKCON ($DFF09E) control bits (write only register)
Page 246: Figure 8-8: Chinon Timing Diagram Cont
Figure 8-8: Chinon Timing diagram cont. - Interface Hardware 237 -...
Page 247: Table 8-5 Disk Subsystem
CIAAPRA/CIABPRB - DISK SELECTION, CONTROL AND SENSING The following Table lists how 8520 chip bits used by the disk subsystem. Bits labelled "PA" are input bits in CIAAPRA ($BFE001). Bits labelled "PB" are output bits located in CIAAPRB ($BFD100). More information on how the 8520 chips operate can be found in Appendix F. Table 8-5: Disk Subsystem Name Function...
Page 248 After turning on the motor, software must further wait for one half second (500ms), or for the DSKRDY* line to go low. DSKSEL3* Select drive 3 (active low). DSKSEL2* Select drive (active low). DSKSEL1* Select drive 1 (active low). DSKSEL0* Select drive 0 (internal drive) (active low).
Page 249: Table 8-6 Dsklen Register ($Dff024)
DISK DMA CHANNEL CONTROL Data is normally transferred to the disk by direct memory access (DMA). The disk DMA is controlled by four items: o Pointer to the area into which or from which the data is to be moved o Length of data to be moved by DMA o Direction of data transfer (read/write) o DMA enable...
Page 250 The hardware requires a special sequence in order to start DMA to the disk. This sequence prevents accidental writes to the disk. In short, the DMAEN bit in the DSKLEN register must be tuned on twice in order to actually enable the disk DMA hardware. Here is the sequence you should follow: 1.
Page 251: Table 8-7 Dskbytr Register
DSKBYTR - DISK DATA BYTE AND STATUS READ (READ-ONLY) This register is the disk-microprocessor data buffer. In read mode, data from the disk is placed into this register one byte at a time. As each byte is received into the register, the DSKBYT bit is set true.
Page 252: Table 8-8 Adkcon And Adkconr Register
Table 8-8: ADKCON and ADKCONR Register Number Name Function SET/CLR Control bit that allows setting or clearing of individual bits without affecting the rest of the register. If bit 15 is a 1, the specified bits are set. If bit 15 is a 0, the specified bits are cleared. PRECOMP1 MSB of Precompensation specifier PRECOMP0...
Page 253: Disk Interrupts
The raw MFM data that must be presented to the disk controller will be twice as large as the unencoded data. The following Table shows the relationship: 1 ---> 01 0 ---> 10 ;if following a 0 0 ---> 00 ;if following a 1 With clever manipulation, the blitter can be used to encode and decode the MFM.
Page 254: The Keyboard
THE KEYBOARD The keyboard is interfaced to the system via the serial shift register on one of the 8520 CIA chips. The keyboard data line is connected to the SP pin, the keyboard clock is connected to the CNT pin. Appendix H contains a full description of the interface. HOW THE KEYBOARD DATA IS RECEIVED The CNT line is used as a clock for the keyboard.
Page 255 Cursor left 50-59 Function keys F1-F10 Help RAW KEYCODES --> 60-67 HEX (KEY CODES FOR QUALIFIER KEYS:) Left shift Right shift Caps lock Control Left ALT Right ALT Left Amiga (or Commodore key) Right Amiga - 246 Interface Hardware -...
Page 256: Limitations Of The Keyboard
F0-FF HEX These key codes are used for keyboard to 68000 communication, and are not associated with a keystroke. They have no key transition flag, and are therefore described completely by 8-bit codes: Reset warning. CTRL-AMIGA-AMIGA has been pressed. The keyboard will wait a maximum of 10 seconds before resetting the machine.
Page 257 All of the keyboards are designed so that phantoms will not happen during normal typing, only when unusual key combinations like the one just described are pressed. Normally, the keyboard will appear to have "N-key rollover," which means that you will run out of fingers before generating a ghost character.
Page 258: Figure 8-9 The A1000 Keyboard, Showing Keycodes In Hex
Figure 8-9: The Amiga 1000 Keyboard, Showing Keycodes in hex Figure 8-10: the Amiga 500/2000 Keyboard, showing Keycodes in hex. - Interface Hardware 249 -...
Page 259: Parallel Input/Output Interface
PARALLEL INPUT/OUTPUT INTERFACE The general-purpose bi-directional parallel interface is a 25-pin connector on the back panel of the computer. This connector is generally used for a parallel printer. For each data byte written to the parallel port register, the hardware automatically generates a pulse on the data ready pin.
Page 260: Setting The Receive Mode
All timing is done on the basis of a "color clock," which is 279.36ns long on NTSC machines and 281.94ns on PAL machines. If the SERPER divisor is set to the number N, then N+1 color clocks occur between samples of the state of the input pin (for receive) or between transmissions of output bits (for transmit).
Page 261: Table 8-9 Serdatr / Adkcon Registers
Table 8-9 shows the definitions of the various bit positions within SERDATR. Table 8-9: SERDATR / ADKCON Registers SERDATR Number Name Function OVRUN OVERRUN bit (Mirror - also appears in the interrupt request register.) Indicates that another byte of data was received before the previous byte was picked up by the processor.
Page 262: How Output Data Is Transmitted
Stop bit if 8 data bits are specified for receive. DB 8 9th data bit if 9 bits are specified for receive. DB7-DB0 Low 8 data bits of received data. Data is TRUE (data you read is the same polarity as the data expected). ADKCON 15 SET/CLR Allows setting or clearing individual bits.
Page 263: Specifying The Register Contents
9 8 7 ------------------------------------------- 0 0 0 0 0 0 0 1 |<-----8 bits data----->| ------------------------------------------- --------------------------> Data gets shifted out this way Figure 8-12: Starting Appearance of SERDAT and Shift Register 9 8 7 ------------------------------------------- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -------->| 1 | ------------------------------------------- 1 bit All zeros from the last shift -...
Page 264: Display Output Connections
The transmission of the start bit is independent of the contents of this register. One start bit is automatically generated before the first data bit (bit 0) is sent. Writing this register starts the data transmission. If this register is written with all zeros, no data transmission is initiated.
Page 265 - 256 Interface Hardware –...
Page 266: Appendix A Register Summary-Alphabetical Order
APPENDIX A REGISTER SUMMARY - ALPHABETICAL ORDER This appendix contains the definitive summary, in alphabetical order, of the register set and the uses of the individual bits. - Appendix A 257 -...
Page 267 The addresses shown here are used by the special chips (called "Agnus", "Denise", and "Paula") for transferring data among themselves. Also, the Copper uses these addresses for writing to the special chip registers. To write to these registers with the 68000, calculate the 68000 address using this formula: 68000 address = (chip address) + $DFF000 For example, for the 68000 to write to ADKCON (address = $09E), the address would be...
Page 268 Agnus/ Read/ Denise/ Register Addresses Write Paula Function -------------------------------------------------------------------- ADKCON Audio, disk, control write ADKCONR Audio, disk, control read BIT# USE -------------------------------------------------------------------- SET/CLR Set/clear control bit. Determines if bits written with a 1 get set or cleared. Bits written with a zero are always unchanged.
Page 269 AUDxLCH 0A0 W A Audio channel x location (high 3 bits) AUDxLCL 0A2 W A Audio channel x location (low 15 bits) This pair of registers contains the 18 bit starting address (location) of audio channel x (x=0,1,2,3) DMA data. This is not a pointer register and therefore needs to be reloaded only if a different memory location is to be outputted.
Page 270 BLTCON0 040 W A Blitter control register 0 BLTCON1 042 W A Blitter control register 1 These two control registers are used together to control blitter operations. There are two basic mode, area and line, which are selected by bit 0 of BLTCON1, as shown below. AREA MODE ("normal") BIT BLTCON0 BLTCON1...
Page 271 BLTCON0 (cont.) LINE DRAW LINE MODE (line draw) BLTCON1 (cont.) LINE DRAW LINE DRAW BIT# BLTCON0 BLTCON1 LINE DRAW LINE DRAW START3 TEXTURE3 LINE DRAW START2 TEXTURE2 LINE DRAW STARTl TEXTURE1 LINE DRAW START0 TEXTURE0 LINE DRAW LINE DRAW LINE DRAW LINE DRAW LINE DRAW LINE DRAW...
Page 272 BLTDDAT Blitter destination data register This register holds the data resulting from each word of blitter operation until it is sent to a RAM destination. This is a dummy address and cannot be read by the micro. The transfer is automatic during blitter operation.
Page 273 BLTxMOD 064 W A Blitter modulo x This register contains the modulo for blitter source (xA,B,C) or destination (x=D). A modulo is a number that is automatically added to the address at the end of each line, to make the address point to the start of the next line.
Page 274 BPLCON0 100 W A D Bit plane control register (misc. control bits) BPLCON1 102 W D Bit plane control register (horizontal scroll control) BPLCON2 104 W D Bit Plane control register (video priority control) These registers control the operation of the bit planes and various aspects of the display.
Page 275 BPLxDAT 110 W D Bit plane x data (parallel-to-serial convert) These registers receive the DMA data fetched from RAM by the bit plane address pointers described above. They may also be written by either microprocessor. They act as a six-word parallel- to-serial buffer for up to six memory bit planes (x=1-6).
Page 276 CLXDAT 00E R D Collision data register (read and clear) This address reads (and clears) the collision detection register. The bit assignments are below. NOTE: Playfield 1 is all odd-numbered enabled bit planes. Playfield 2 is all even-numbered enabled bit planes BIT# COLLISIONS REGISTERED -------------------------------------- not used...
Page 277 COPCON 02E W A Copper control register This is a 1-bit register that when set true, allows the Copper to access the blitter hardware. This bit is cleared by power-on reset, so that the Copper cannot access the blitter hardware. NAME FUNCTION CDANG...
Page 278 COPINS (cont.) MOVE WAIT UNTIL SKIP IF RD15 BFD * BFD * RD14 RD13 RD12 RD11 RD10 RD09 RD08 RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 =First instruction register =Second instruction register =Destination address for MOVE instruction. Fetched during IR1 time, used during IR2 time on RGA bus. =RAM data moved by MOVE instruction at IR2 time directly from RAM to the address given by the DA field.
Page 279 COPINS (cont.) There are two indirect jump registers, COP1LC and COP2LC. These are 18- bit pointer registers whose contents are used to modify the program counter for initialization or jumps. They are transferred to the program counter whenever strobe addresses COPJMP1 or COPJMP2 are written. In addition, COP1LC is automatically used at the beginning of each vertical blank time.
Page 280 DDFSTOP 094 W A Display data fetch stop (horiz. position) DDFSTRT 092 W A Display data fetch start (horiz. position) These registers control the horizontal timing of the beginning and end of the bit plane DMA display data fetch. The vertical bit plane DMA timing is identical to the display windows described above.
Page 281 DMACON 096 W A D P DMA control write (clear or set) DMACONR 002 R A P DMA control (and blitter status) read This register controls all of the DMA channels and contains blitter DMA status bits. FUNCTION DESCRIPTION SET/CLR Set/clear control bit.
Page 282 DSKDAT Disk DMA data write DSKDATR Disk DMA data read (early read dummy address ) This register is the disk DMA data buffer. It contains two bytes of data that are either sent (written) to or received (read) from the disk. The write mode is enabled by bit 14 of the LENGTH register.
Page 283 INTENA 09A W P Interrupt enable bits (clear or set bits) INTENAR 01C R P Interrupt enable bits (read) This register contains interrupt enable bits. The bit assignment for both the request and enable registers is given below. BIT# FUNCT LEVEL DESCRIPTION --------------------------------------------------------...
Page 284 JOY0DAT 00A R D Joystick-mouse 0 data (left vertical, horizontal) JOY1DAT 00C R D Joystick-mouse 1 data (right vertical, horizontal) These addresses each read a pair of 8-bit mouse counters. 0=left controller pair, 1=right controller pair (four counters total). The bit usage for both left and right addresses is shown below.
Page 285 JOYTEST 036 W D Write to all four joystick-mouse counters at once. Mouse counter write test data: BIT# 15,14,13,12,11,10,09,08 07,06,05,04,03,02,01,00 ---------------------------------------------------- 0DAT Y7 Y6 Y5 Y4 Y3 Y2 xx xx X7 X6 X5 X4 X3 X2 xx xx 1DAT Y7 Y6 Y5 Y4 Y3 Y2 xx xx X7 X6 X5 X4 X3 X2 xx xx POT0DAT 012 R P Pot counter data left pair (vert,horiz)
Page 286 SERDAT 030 W P Serial port data and stop bits write (transmit data buffer) This address writes data to a transmit data buffer. Data from this buffer is moved into a serial shift register for output transmission whenever it is empty.
Page 287 SERPER 032 W P Serial port period and control This register contains the control bit LONG referred to above, and a 15-bit number defining the serial port baud rate. If this number is N, then the baud rate is 1 bit every (N+1) * 0.2794 microseconds. BIT# FUNCTION --------------------------------------------------------------...
Page 288 SPRxPTH 120 W A Sprite x pointer (high 3 bits) SPRxPTL 122 W A Sprite x pointer (low 15 bits) This pair of registers contains the 18-bit address of sprite x (x=0,1,2,3,4,5,6,7) DMA data. These address registers must be initialized by the processor or Copper every vertical blank time.
Page 289 - 280 Appendix A -...
Page 290: Appendix B Register Summary-Address Order
APPENDIX B REGISTER SUMMARY ADDRESS ORDER This appendix contains information about the register set in address order. - Appendix B 281 -...
Page 291 The following codes and abbreviations are used in this appendix: & Register used by DMA channel only. Register used by DMA channel usually, processors sometimes. Address register pair. Must be an even address pointing to chip memory. Address not wriTable by the Copper. Address not wriTable by the Copper unless the "copper danger bit", COPCON is set true.
Page 292 NAME ADD R/W CHIP FUNCTION ----------------------------------------------------------------------- BLTDDAT & *000 ER A Blitter destination early read (dummy address) DMACONR *002 R P DMA control (and blitter status) read VPOSR *004 R Read vert most signif. bit (and frame flop) VHPOSR *006 R Read vert and horiz.
Page 293 -076 -078 -07A -07C DSRSYNC -07E W P Disk sync pattern register for disk read COP1LCH + 080 W A Coprocessor first location register (high 3 bits) COP1LCL + 082 W A Coprocessor first location register (low 15 bits) COP2LCH + 084 W A Coprocessor second location register (high 3 bits)
Page 294 BPL1PTH + 0E0 W A Bit plane 1 pointer (high 3 bits) BPL1PTL + 0E2 W A Bit plane 1 pointer (low 15 bits) BPL2PTH + 0E4 W A Bit plane 2 pointer (high 3 bits) BPL2PTL + 0E6 W A Bit plane 2 pointer (low 15 bits) BPL3PTH + 0E8 W A Bit plane 3 pointer (high 3 bits)
Page 295 SPR0PTH + 120 W A Sprite 0 pointer (high 3 bits) SPR0PTL + 122 W A Sprite 0 pointer (low 15 bits) SPR1PTH + 124 W A Sprite 1 pointer (high 3 bits) SPR1PTL + 126 W A Sprite 1 pointer (low 15 bits) SPR2PTH + 128 W A Sprite 2 pointer (high 3 bits)
Page 296 SPR6POS % 170 W A D Sprite 6 vert-horiz start position data SPR6CTL % 172 W A D Sprite 6 vert stop position and control data SPR6DATA % 174 W D Sprite 6 image data register A SPR6DATB % 176 W D Sprite 6 image data register B SPR7POS % 178 W A D...
Page 297 - 288 Appendix B -...
Page 298: Appendix C Custom Chip Pin Allocation List
APPENDIX C CUSTOM CHIP PIN ALLOCATION LIST NOTE: * Means an active low signal. - Appendix C 289 -...
Page 299 AGNUS PIN ASSIGNMENT PIN # DESIGNATION FUNCTION DEFINITION 01-09 D8-D0 Data bus lines 8 to 0 +5 Volt RES* System reset INT3* Interrupt level 3 DMAL DMA request line BLS* Blitter slowdown DBR* Data bus request ARW* Agnus RAM write 17-24 RGA8-RGA1 Register address bus 8-1...
Page 300 PAULA PIN ASSIGNMENT DESIGNATION FUNCTION DEFINITION 01-07 D8-D2 Data bus lines 8 to 2 Ground 09-10 D1-D0 Data bus lines 1 and 0 RES* System reset DMAL DMA request line 13-15 IPL0*-IPL2 Interrupt lines 0-2 INT2* Interrupt level 2 INT3* Interrupt level 3 INT6* Interrupt level 6...
Page 301 FAT AGNUS PIN ASSIGNMENT DESIGNATION FUNCTION DEFINITION 01-14 RD1S-RD2 Register bus lines 15 to 2 INT3* Blitter ready interrupt DMAL Request audio/disk DMA Register bus line 1 RST* Reset BLS* Blitter slowdown DBR* Data bus request DRAM Write/Read Processor Write/Read RGEN* RG Enable Address Strobe...
Page 302: Appendix D System Memory Map
APPENDIX D SYSTEM MEMORY MAP Appendix D 293 -...
Page 303 A true software memory map, showing system utilization of the various sections of RAM and free space is not provided, or possible with the Amiga. All memory is dynamically allocated by the memory manager, and the actual locations may change from release-to-release, machine-to-machine or boot-to-boot (see the exec/AllocMem function for details).
Page 304: Appendix E Interfaces
APPENDIX E INTERFACES This appendix consists of four distinct parts, related to the way in which the Amiga talks to the outside world. The first part specifies the pinouts of the externally accessible connectors and the power available at each connector. It does not, however, provide timing or loading information. The second part briefly describes the functions of those pins whose purpose may not be evident.
Page 305 The third and fourth parts are primarily for the use of the systems programmer and should generally not be utilized by applications programmers. Systems software normally is conFigured to handle the setting of particular signals, no matter how the physical connections may change. In other words, if you have a version of the system software that matches the revision level of the machine (normally a true condition), when you ask that a particular bit be set, you don't care which port that bit is connected to.
Page 306 PARALLEL (CENTRONICS) PORT -------------------------- 1000 500/2000 Commodore PC's ---- -------- -------------- DRDY* STROBE* STROBE* Data 0 Data 0 Data 0 Data 1 Data 1 Data 1 Data 2 Data 2 Data 2 Data 3 Data 3 Data 3 Data 4...
Page 307 RF Monitor ...8 PIN DIN (J2) A1000 only --------------------------------------- 1 N.C. 2 GND 3 AUDIO LEFT 4 COMP VIDEO 5 GND 6 N.C. 7 +12 VOLT POWER 8 ADIO RIGHT DISK EXTERNAL ...DB23 FEMALE ---------------------------- For A500, A1000, and A2000 with A2000 differences noted. RDY* 13 SIDEB* DKRD*...
Page 308 RAMEX . 60 PIN EDGE (156) (P1) A1000 only ---------------------------------------------- 2 D15 3 +5 4 D12 5 gnd 6 D11 7 +5 8 D8 9 gnd 10 D7 11 +5 12 D4 13 gnd 14 D3 15 +5 16 D0 17 gnd 18 DRA4 DRA3...
Page 309 EXPANSION ...86 PIN EDGE (.1) (P2) ---------------------------------- A500 A1000 A2000 A2000b FUNCTION ---- ----- ----- ------ -------- ground ground ground ground +5VDC +5VDC No Connect -5VDC No Connect 28MHz Clock +12VDC No Connect /COPCFG (Configuration Out) CONFIG IN, Grounded Ground /C3 Clock CDAC Clock /C1 Clock...
Page 310 EXPANSION ...86 PIN EDGE (.1) (P2) (cont.) ------------------------------------------------------ A500 A1000 A2000 A2000b FUNCTION ---- ----- ----- ------ -------- /VMA /HLT /CBR Ground /BGACK /CBG /DTACK /LDS /UDS Ground Ground JOYSTICKS ...DB9 male --------------------- USAGE JOYSTICK MOUSE ----- -------- ----- FORWARD* (MOUSE V) BACK* (MOUSE H)
Page 311 ************** PART 2 MORE OUTSIDE WORLD ******************** PARALLEL INTERFACE CONNECTOR SPECIFICATION The 25-pin D-type connector with pins (DB25P=male for the A1000, female for A500/A2000 and IBM compatibles) at the rear of the Amiga is nominally used to interface to parallel printers. In this capacity, data flow from the Amiga to the printer.
Page 312 PARALLEL CONNECTOR INTERFACE TIMING, OUTPUT CYCLE PA<7:0>_____ ____________________________________________ ____ PB<7:0>_____X____________________________________________X____ |<-- T1 --->| |<--------- T2 -------->| DRDY* _________________V V____________________________ Output data ready |________| |<- T3 ->| |<--- T4 ---->| ACK* ________________________________|<- T5 -->|_____________ Output data acknowledge Microseconds Min Typ Max --- --- --- T1: 4.3 -x- 5.3 Output data setup to ready delay.
Page 313 SERIAL INTERFACE CONNECTOR SPECIFICATION This 25-pin D-type connector with sockets (DB255=female) is used to interface to RS-232-C standard signals. Signal names correspond to those used in other places in this appendix, when possible. WARNING: Pin on the R5232 connector other than these standard ones described below may be connected to power or other non-R5232 standard signals.
Page 314 SERIAL INTERFACE CONNECTOR ELECTRICAL CHARACTERISTICS OUTPUTS MIN TYP MAX ------- --- --- --- Vo(-): 13.2 -x- -2.5 Negative output voltage range Vo(+): 13.2 Positive output voltage range 10.0 Output current INPUTS MIN TYP MAX ------ --- --- --- Vi(+): 3.0 -x- 25.0 Positive input voltage range Vi(-): 25.0 -x- 0.5...
Page 315 GAME CONTROLLER INTERFACE TO MOUSE/TRACKBALL QUADRATURE INPUTS A mouse or trackball is a device that translates planar motion into pulse trains. Quadrature techniques are employed to preserve the direction as well as magnitude of displacement. The registers JOY0DAT and JOY1DAT become counter registers, with y displacement in the high byte and x in the low byte.
Page 316 GAME PORT INTERFACE TO DIGITAL JOYSTICKS A joystick is a device with four normally opened switches arranged 90 degree apart. The JOY[0/1]DAT registers become encoded switch input port as follows: Forward: bit9 xor bit#8 Left: bit9 Back: bit1 xor bit0 Right: bit1 Data is encoded to facilitate the mouse/trackball operating mode.
Page 317 CONNECTOR PIN USAGE FOR FIRE BUTTON INPUTS PIN MNEMONIC DESCRIPTION --- -------- ----------- FIRE* Left mouse button/fire button ground GAME PORT INTERFACE TO PROPORTIONAL CONTROLLERS Resistive (potentiometer) element linear taper proportional controllers are supported up to 528k Ohms max (470k +/- 10% recommended).
Page 318 CONNECTOR PIN USAGE FOR PROPORTIONAL INPUTS PIN MNEMONIC DESCRIPTION HARDWARE REGISTER/NOTES --- -------- ----------- ----------------------- XBUT Extra Button Unused LBUT* Left button See Digital Joystick RBUT* Right button See Digital Joystick POTX X analog in POT[0/1]DAT<7:0>, POTGO, POTINP Unused 125ma max, 200 ma surge Ground POTY Y analog in...
Page 319 EXTERNAL DISK INTERFACE CONNECTOR SPECIFICATION The 23-pin D-type connector with sockets (DB23S) at the rear of the Amiga is nominally used to interface to MFM devices. EXTERNAL DISK CONNECTOR PIN ASSIGNMENT (J7) PIN NAME NOTES --- ---- ----- RDY* If motor on, indicates disk installed and up to speed.
Page 320 $0000 0000 - no drive present. $FFFF FFFF - Amiga standard 3.25 diskette. $5555 5555 - 48 TPI double-density, double-sided. As with other peripheral ID's, users should contact Commodore-Amiga for ID assignment. The serial input data is active low and must therefore be inverted to be consistent with the above Table.
Page 321 ************** PART 3 - INTERNAL CONNECTORS ******************* DISK INTERNAL ...34 PIN RIBBON (J10) ------------------------------------ 1 GND 18 DIRB 2 CHNG* 19 GND 3 GND 20 STEPB* 4 MTROD* led) 21 GND 5 GND 22 DKWDB* 6 N.C. 23 GND 7 GND 24 DKWEB* 8 IND B * 25 GND...
Page 322 PA3..com line DSR* PA2..SEL Centronics control PA1..POUT +--- paper out -------------+ PA0..BUSY | +--busy-----------------+ | SPBUSY | +- commodore serial bus-+ | CNT..POUT + --commodore serial bus ---+ PB7..MTR* motor PB6..SEL3* select external 3rd drive PB5..SEL2* select external 2nd drive PB4..SEL1*...
Page 323 PORT 0 __________________ POTOX 5 o_/________________________ 9 o__/___________ \____________/ POTOY ______V_____________V______ | POT0Y | POT0Y | POT0DAT | COUNTER | COUNTER | DFF012 |_____________|_____________| PORT 1 __________________ POTOX o_/________________________ o__/___________ \____________/ POTOY ______V_____________V______ | POT1Y | POT1X | COUNTER | COUNTER | POT1DAT | LATCH | LATCH...
Page 324 PORT 1 __________________ PORT 2 __________________ \__|_________/ \__|_________/ _________| |FIRE 0\ ______________________________________| FIRE 1\ ___|___________________________________________________ | FIRE | FIRE | | PRA |$BFE001 |______|______|______|______|______|______|______|______| |______________| _______________________________________________________ |Data |direc- |______|______|______|______|______|______|______|______| tion DDRA $BFE201 READING FIRE BUTTONS - Appendix E 315 -...
Page 325 ____________________________________________ | VPOSR read only | DFF004 |____________________________________________| ____________________________________________ | VHPOSR read only | DFF006 |____________________________________________| ____________________________________________ | BPLCON0 write only | DFF104 |__|__|__|__|__|__|__|__|__|__|__||_|__|__|__| |________Light Pen Enable ____________________________________________ | POT1NP read only | DFF016 (Bit 8) |__|__|__|__|__|__|__|__|__|__|__|__|__|__|__| PEN PRESS=POTOX |___________________ _________________ o_/_____| \_|_________/...
Page 326: Appendix F Complex Interface Adapters
APPENDIX F COMPLEX INTERFACE ADAPTERS This appendix contains information about the 8520 peripheral interface adapters. 8520 COMPLEX INTERFACE ADAPTOR CIA) CHIPS Each Amiga system contains two 8520 Complex Interface Adaptor (CIA) chips. Each chip has 16 general purpose input/output pins, plus a serial shift register, three timers, an output pulse pin and an edge detection input.
Page 327 CIAA Address Map ---------------- Byte Register Data bits Address Name ------------------------------------------------------------------ BFE001 /FIR1 /FIR0 /RDY /TK0 /WPRO /CHNG /LED OVL BFE101 Parallel port BFE201 ddra Direction for port A (BFE001);1 output (set to 0x03) BFE301 ddrb Direction for port B (BFE101);1 output (can be in/out) BFE401 talo CIAA timer A low byte (.715909 Mhz NTSC;...
Page 328: Chip Register Map
CHIP REGISTER MAP Each 8520 has 16 registers that you may read or write. Here is the list of register and the access addresses of each within the memory space dedicated to the 8520: Register RS3 R52 RS1 RS0 (hex) NAME MEANING ------------------------------------------------------------ Peripheral data register A...
Page 329: Register Functional Description
REGISTER FUNCTIONAL DESCRIPTION I/O PORTS (PRA, PRB, DDRA, DDRB) Ports A and B each consist of an 8-bit peripheral data register (PR) and an 8-bit data direction register (DDR). If a bit in the DDR is set to a 1, the corresponding bit position in the PR becomes an output. If a DDR bit is set to a 0, the corresponding PR bit is defined as an input.
Page 330 The latch is also called a prescalar in that it represents the countdown value which must be counted before the timer reaches an underflow (no more counts) condition. This latch (prescalar) value is a divider of the input clocking frequency. The timers can be used independently or linked for extended operations.
Page 331: Input Modes
FORCE LOAD A strobe bit allows the timer latch to be loaded into the timer counter at any time, whether the timer is running or not. INPUT MODES Control bits allow selection of the dock used to decrement the timer. Timer A can count 02 clock pulses or external pulses applied to the CNT pin.
Page 332: Time Of Day Clock
TIME OF DAY CLOCK TOD consists of a 24-bit binary counter. Positive edge transitions on this pin cause the binary counter to increment. The TOD pin has a passive pull-up on it. A programmable alarm is provided for generating an interrupt at a desired time.
Page 333: Serial Shift Register (Sdr)
SERIAL SHIFT REGISTER (SDR) The serial port is a buffered, 8-bit synchronous shift register. A control bit selects input or output mode. In the Amiga system one shift register is used for the keyboard, and the other is unassigned. Note that the RS-232 compatible serial port is controlled by the Paula chip;...
Page 334: Bidirectional Feature
BIDIRECTIONAL FEATURE The bi-directional capability of the shift register and CNT clock allows many 8520s to be connected to a common serial communications bus on which one 8520 acts as a master, sourcing data and shift clock while all other 8520 chips act as slaves.
Page 335: Read Interrupt Control Register
If bit 7 is a 1, then any bit 6-0 in your own mask byte which is set to a 1 sets the corresponding bit in the MASK register. Any bit that you have set to a 0 causes the MASK register bit to remain in its current state.
Page 336: Control Registers
CONTROL REGISTERS There are two control registers in the 8520, CRA and CRB. CRA is associated with Timer A and CRB is associated with Timer B. The format of the registers is as follows: CONTROL REGISTER A BIT NAME FUNCTION START 1 = start Timer A, 0 - top Timer A.
Page 337: Bit Map Of Register Cra
BIT MAP OF REGISTER CRA REG# NAME UNUSED SPMODE INMODE LOAD RUNMODE OUTMODE PBON START unused 0=input 0=02 1=force 0=cont. 0=pulse 0=PB60FF 0=stop unused 1=output 1=CNT load 1=one- 1=toggle 1-PB60N 1=start (strobe) shot |<------------Timer A Variables------------->| All unused register bits are unaffected by a write and forced to 0 on a read.
Page 338: Bit Map Of Register Crb
BIT MAP OF REGISTER CRB NAME ALARM INMODE LOAD RUNMODE OUTMODE PBON START 0=TOD 00-02 1=force 0=cont. 0=pulse 0=PB70FF 0=stop 1=Alarm 01=CNT load 1=one- 1=toggle 1=PB70N 1=start 10=Timer A (strobe) shot 11=CNT+ Timer A <--------------Timer B Variables----------------> All unused register bits are unaffected by a write and forced to 0 on a read.
Page 339 PA4..com line CTS* PA3..com line DSR* PA2..SEL centronics control PA1..POUT paper out ---+ PA0..BUSY busy -----+ | SP...BUSY commodore -+ | CNT..POUT commodore ---+ PB7..MTR* motor PB6..SEL3* select external 3rd drive PB5..SEL2* select external 2nd drive PB4..SEL1* select external 1st drive PB3..SEL0*...
Page 340 ; A complete 8520 timing example. This blinks the power light at (exactly) ; 3 millisecond intervals. It takes over the machine, 50 watch out! ; The base Amiga crystal frequencies are: NTSC 28.63636 MHz 28.37516 MHz ; The two 16 bit timers on the 8520 chips each count down at 1/10 the CPU ;...
Page 341: Hardware Connection Details
HARDWARE CONNECTION DETAILS The system hardware selects the CIAs when the upper three address bits are 101. Furthermore, CIAA is selected when A12 is low, A13 high; CIAB is selected when A12 is high, A13 low. CIAA communicates on data bits 7-0, CIAB communicates on data bits 15-8.
Page 342 RSRS0 - ADDRESS INPUTS The address inputs select the internal registers as described by the register map. DB7-DB0 - DATA BUS INPUTS/OUTPUTS The eight data bus output pins transfer information between the 8520 and the system data bus. These pins are high impedance inputs unless CS is low and R/W and 02 are high, to read the device.
Page 343 - 334 Appendix F -...
Page 344: Appendix G Autoconfig
$40 words ($80 bytes) of the board. This identification information includes the size of the board, its address space preferences, type of board (memory or other), and a unique Hardware Manufacturer Number assigned by Commodore Amiga Technical Support, West Chester, Pennsylvania.
Page 345: Debugging Autoconfig Boards
All commercial expansion slot boards for the Amiga must implement the AUTOCONFIG protocol. More in-depth machine-specific information on the design and implementation of AUTOCONFIG boards is available from Commodore Amiga Technical Support. The Amiga operating system contains support for matching up disk-based drivers with AUTO-CONFIG boards.
Page 346: Address Specification Table
from the bus to the board. This allows the board to respond to the AUTOCONFIG process. When the switch is set the other way, it should be wired such that the input to the board is forced high This will disable the AUTOCONFIG of the board. Set the switch so that the CONFIGIN* line is forced high, then bring up the system.
Page 347: Figure G-1 How To Read The Address Specification Table
Board Offset ($00/02) Description of nibbles R/W info \___ ___/ \___ ___/ Nibble at $E80000 Nibble at $E80002 Figure G-1: How to read the Address Specification Table NOTE The bit numbering ( 7 6 5 4 3 2 1 0 ) is for use when two nibbles are to be interpreted together as a byte.
Page 348 Hi nibble Lo nibble (Not developer number!) NOTE Manufacturer number is assigned by Commodore Amiga Technical Support in West Chester, Pennsylvania (CATS). Contact CATS for further information. ($18/1A) Optional aerial #, 1st byte (msb) ($1C/lE) Optional serial #, 2nd byte...
Page 349 OFFSET: Address 1 Address 2 Description (cont.) ------------------------------------------------------------------------- (S40/42) Write Read Not Inverted \_ Interrupt enable Interrupt enable \____ User definable Undefined \_______ Local reset Must be 0 \__________ User definable Undefined \_____________ User definable INT2 pending \________________ User definable INT6 pending \___________________ User definable INT7 pending...
Page 350 * Examine all AUTOCONFIG(tm) boards in the system include "exec/types.h" include "libraries/configvars.h" struct Library *OpenLibrary(); struct ConfigDev *FindConfigDev(); struct Library *ExpansionBase; void main() struct ConfigDev *myCD=0; ExpansionBase=OpenLibrary("expansion.library",0L); while(myCD=FindConfigDev(myCD,-1L,-1L)) /* search for any ConfigDev */ printf("\n---ConfigDev structure found at location $%1x---\n",myCD); /* These valuses are read directly from the board */ printf("er Manufacturer =");...
Page 351 - 342 Appendix G -...
Page 352: Appendix H Keyboard
APPENDIX H KEYBOARD This appendix contains the keyboard interface specification for A1000, A500 and A2000. The keyboard plugs into the Amiga computer via a cable with four primary connections. The four wires provide 5-volt power, ground, and signals called KCLK (keyboard clock) and KDAT keyboard data).
Page 353: Keyboard Communications
KEYBOARD COMMUNICATIONS The keyboard transmits 8-bit data words serially to the main unit. Before the transmission starts, both KCLK and KDAT are high. The keyboard starts the transmission by putting out the first data bit (on KDAT), followed by a pulse on KCLK (low then high); then it puts out the second data bit and pulses KCLK until all eight data bits have been sent.
Page 354: Keycodes
KEYCODES Each key has a keycode associated with it (see accompanying Table). Keycodes are always 7 bits long. The eighth bit is a "key-up"/"key-down" flag; a 0 (high level) means that the key was pushed down, and a 1 (low level) means the key was released (the CAPS LOCK key is different –...
Page 355: Out-Of-Sync" Condition
"OUT-OF-SYNC" CONDITION Noise or other glitches may cause the keyboard to get out of sync with the computer. This means that the keyboard is finished transmitting a code, but the computer is somewhere in the middle of receiving it. If this happens, the keyboard will not receive its handshake pulse at the end of its transmission.
Page 356 The first thing the keyboard does on power-up is to perform a self-test. This involves a ROM checksum test, simple RAM test, and watchdog timer test. Whenever the keyboard is powered up (or restarted - see below), it must not transmit anything until it has achieved synchronization with the computer.
Page 357: Reset Warning
RESET WARNING NOTE Available on some A1000 and A2000 keyboards. You cannot rely on this feature for all Amiga’s. The keyboard has the additional task of resetting the computer on the command of the user. The user initiates Reset Warning by simultaneously pressing the CTRL key and the two "AMIGA"...
Page 358: Special Codes
After releasing KCLK, the keyboard jumps to its start-up code (internal RESET). This will initialize the keyboard in the same way as cold power-on. NOTE The keyboard must resend the "powerup key stream"! SPECIAL CODES The special codes that the keyboard uses to communicate with the main unit are summarized here.
Page 359: Matrix Table
MATRIX Table Row 5 Row 4 Row 3 Row 2 Row 1 Row 0 Column (Bit 7) (Bit 6) (Bit 5) (Bit 4) (Bit 3) (Bit 2) +-------+-------+-------+-------+-------+-------+ |(spare)|(spare)|(spare)|(spare)|(spare)|(spare)| (PD.7)| (0E) | (1C) | (2C) | (47) | (48) | (49) +-------+-------+-------+-------+-------+-------+ |<SHIFT>| CAPS (PD.6)|note 1 |note 2 | LOCK...
Page 360 Row 5 Row 4 Row 3 Row 2 Row 1 Row 0 Column (Bit 7) (Bit 6) (Bit 5) (Bit 4) (Bit 3) (Bit 2) +-------+-------+-------+-------+-------+-------+ (PC.4)|note 3 | | (3D) | (3A) | (29) | (19) | 0A) | (56) +-------+-------+-------+-------+-------+-------+ |(spare)| "...
Page 361 - 352 Appendix H -...
Page 362: Appendix I External Disk Connector Interface Spec
APPENDIX I EXTERNAL DISK CONNECTOR INTERFACE SPECIFICATION GENERAL The 23-pin female connector at the rear of the main computer unit is used to interface to and control devices that generate and receive MFM data. This interface can be reached either as a resource or under the control of a driver. The following pages describe the interface in both cases.
Page 363: Summary Table
SUMMARY Table Pin # Name Note RDY- ID and ready DKRD- MFM input GRND GRND GRND GRND GRND MTRXD- Motor control. SEL2B- Select drive 2 DRESB- Reset CHNG- Msk changed 540 mA average 870 mA surge SIDEB- Side 1 if low WRPRO- Write protect TK0-...
Page 364: Signals When Driving A Disk
SIGNALS WHEN DRIVING A DISK The following describes the interface under driver control. SEL1B-, SEL2B-, SEL3B- Select lines for the three external disk drives active low. A selected drive pulls this signal low whenever its read-write head is on track 00. RDY- When a disk drive's motor is on, this line indicates the selected disk is installed and rotating at speed.
Page 365 DKWEB- (Pin #16) This signal causes a selected drive to start writing data (provided by DKWDB-) onto the disk. CHNG- (Pin #11) A selected drive will drive this signal low whenever its internal "disk change" latch is set. This latch is set when the drive is first powered on, or whenever there is no diskette in the drive.
Page 366: Device I.d
Device I.D. This interface supports a method of establishing the type of disk(s) attached. The I.D. sequence is as follows. 1. Drive MTRXD- low. 2. Drive SELxB- low 3. Drive SELxB- high. 4. Drive MTRXD- high. 5. Drive SELxB- low 6.
Page 367 - 358 Appendix I -...
Page 368: Appendix J Hardware Example Include File
APPENDIX J HARDWARE EXAMPLE INCLUDE FILE This appendix contains an include file that maps the hardware register names, given in Appendix A and Appendix B, to names that can be resolved by the standard include files. Use of these names in code sections of this manual places the emphasis on what the code is doing, rather than getting bogged down in include file names.
Page 369 IFND HARDWARE_HW_EXAMPLES_I HARDWARE_HW_EXAMPLES_I Filename: hardware/hw_examples.i $Release: 1.3 $ (C) Copyright 1985,1986,1987,1988,1989 Commodore-Amiga, Inc. All Rights Reserved ************************************************************************** IFND HARDWARE_CUSTOM_I INCLUDE "hardware/custom.i" ENDC ************************************************************************** * This include file is designed to be used in conjunction with the hardware * manual examples. This file defines the register names based on the * hardware/custom.i definition file.
Page 370 STRHOR atrhor ; " " STRLONG atrlong ; " " DIWSTRT diwatrt ; " " DIWSTOP diwatop ; " " DDFSTRT ddfatrt ; " " DDFSTOP ddfatop ; " " DMACON dmacon ; " " INTENA intena ; " " INTREQ intreq ;...
Page 371 ADKCON adkcon ; Just capitalization AUD0LC aud0 AUD0LCH aud0 AUD0LCL aud0+$02 AUD0LEN aud0+$04 AUD0PER aud0+$06 AUD0VOL aud0+$08 AUD0DAT aud0+$0A AUD1LC aud1 AUD1LCH aud1 AUD1LCL aud1+$02 AUD1LEN aud1+$04 AUD1PER aud1+$06 AUD1VOL aud1+$08 AUD1DAT aud1+$0A AUD2LC aud2 AUD2LCH aud2 AUD2LCL aud2+$02 AUD2LEN aud2+$04 AUD2PER aud2+$06...
Page 372 DPL1DATA bpldat+$00 DPL2DATA bpldat+$02 DPL3DATA bpldat+$04 DPL4DATA bpldat+$06 DPL5DATA bpldat+$08 DPL6DATA bpldat+$0A * Sprite control registers SPR0PT Sprpt+$00 SPR0PTH SPR0PT+$00 SPR0PTL SPR0PT+$02 SPR1PT sprpt+$04 SPR1PTH SPR1PT+$00 SPR1PTL SPR1PT+$02 SPR2PT sprpt+$08 SPR2PTH SPR2PT+$00 SPR2PTL SPR2PT+S02 SPR3PT sprpt+$0C SPR3PTH SPR3PT+$00 SPR3PTL SPR3PT+$02 SPR4PT sprpt+$10 SPR4PTH...
Page 373 SPR5POS spr+$28 SPR5CTL SPR5POS+ad_ctl SPR5DATA SPR5POS+Ad_dataa SPR5DATB SPR5P05+$06 ; should use ad_datab SPR6POS spr+$30 SPR6CTL SPR6POS+ad_ctl SPR6DATA SPR6POS+sd_dataa SPR6DATB SPR6P05+$06 ; should use sd_datab SPR7POS spr+$38 SPR7CTL SPR7POS+sd_ctl SPR7DATA SPR7POS+sd_dataa SPR7DATB SPR7P05+$06 ; should use ad_datab * Color registers... COLOR00 color+$00 COLOR01 color+$02...
Page 374: Glossary
GLOSSARY AGNUS One of the three main Amiga custom chips. Contains the blitter, copper, and DMA circuitry. ALIASING DISTORTION A side effect of sound sampling, where two additional frequencies are produced, distorting the sound output. ALT KEYS Two keys on the keyboard to the left and right of the Amiga keys. AMIGA KEYS Two keys on the keyboard to the left and right of the space bar.
Page 375 BITPLANE A contiguous series of display memory words, treated as if it were a rectangular shape. BIT-PLANE ANIMATION A means of animating the display by moving around blocks of playfield data with the blitter. BLANKING INTERVAL Time period when the video beam is outside the display area. BLITTER DMA channel used for data copying and line drawing.
Page 376 COORDINATES A pair of numbers shown in the form (x,y), where x is an offset from the left side of the display or display window and y is an offset from the top. COPPER Display-synchronized coprocessor that resides on one of the Amiga custom chips and directs the graphics display.
Page 377 EQUAL-TEMPERED SCALE A musical scale where each note is the 12th root of 2 above the note below it. EXEC Low-level primitives that support the AmigaDOS operating system. FAST MEMORY Memory not accessible by the custom chips. Care must be taken to present only chip memory address to the custom chips.
Page 378 MIDI A standardized musical instrument interface used by many musical instruments. MICROSECOND (US) One millionth of second (1/1,000,000). MILLISECOND (MS) One thousandth of second (1/1,000). MINTERM One of eight possible logical combinations of data bits from three different data sources. MODULO A number defining which data in memory belongs on each horizontal line of the display.
Page 379 PITCH The quality of a sound expressed as its highness or lowness. PIXEL One of the small elements that makes up the video display. The smallest addressable element in the video display. PLAYFIELD One of the basic elements in Amiga graphics; background for all other display elements. PLAYFIELD OBJECT Subsection of a playfield that is used in playfield animation.
Page 380 SCROLLING Moving a playfield smoothly in a vertical or horizontal direction. SERIAL PORT A connector on the back of the Amiga used to attach modems and other serial add-ons. Giving a bit the value of 1. SHARED MEMORY The RAM used in the Amiga for both display memory and executing programs. SPRITE Easily movable graphics object that is produced by one of the eight sprite DMA channels and is independent of the playfield display.

This manual is also suitable for:

Amiga a500 Amiga a2000

Commodore Amiga A1000 Hardware Reference Manual

Chapter 1 INTRODUCTION

Chapter 2 COPROCESSOR HARDWARE

Chapter 3 PLAYIELD HARDWARE

Chapter 4 SPRITE HARDWARE

Chapter 5 AUDIO HARDWARE

Chapter 6 BLITTER HARDWARE

Chapter 7 SYSTEM CONTROL HARDWARE

Chapter 8 INTERFACE HARDWARE

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REFERENCE MANUAL

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Summary of Contents for Commodore Amiga A1000