Commodore Amiga A500 Technical Reference Manual page 165

Reference
FUNCTIONAL
DESCRIPTION
Host Interface
ST506 Hard Disk
Controller (HDC)
●
8727 DMA Specification
● Amiga Expansion Architecture Manual
● Motorola 68000 Technical Manual
●
Western Digital WD33C93 SCSI Chip Manual
●
American National Standard Committee X3T9.2 SCSI Specifica-
tion
The Amiga Hard Disk Controller basically consists of three main sub-
sections:
●
Host Interface
●
ST506 Hard Disk Controller (HDC)
●
SCSI Controller
The host interface is 68000 compatible with direct memory access
and full auto-config capability. Data transfers to and from the host
are usually made via DMA thereby allowing real time date transfer
rates of 1.6us/byte for the ST506 interface and up to 800ns/byte
for SCSI. Addressing for DMA operations is provided by three exter-
nal address counters. Before any DMA operation can be performed
each counter must be pre-set and thereafter will be incremented
automatically. Information on initializing the DMA appears later in
this section.
The DMA is a Commodore custom LSI chip (8727) with byte to
word funneling and a built in 64 byte FIFO. The internal 64 byte
FIFO permits real time data transfer to and from the host without
holding the bus for an entire sector transfer. This provides very
effective utilization of the bus. The average bus requirement for the
transfer of an entire sector is 8.9|jls once every 512\is. This
amounts to only 17% over for CPU and other bus masters.
The interface logic also provides full auto-config and all I/O decode.
For electrical specification and detailed timings refer to Amiga ex-
pansion architecture manual.
The ST506 Hard Disk controller is an intelligent background
controller capable of high level command interpretation and support
of up two ST506 hard disk units. This controller will be refered to
in this document as the HDC or the Hard Disk Controller. The
processor for the HDC is a Z80A CPU, with up to 8K of PROM for
firmware and 1K of RAM for variable data. Collectively, the above
components constitute the "intelligence" of the controller.
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