Commodore Amiga A500 Technical Reference Manual
  1. Manuals
  2. Brands
  3. Commodore Manuals
  4. Desktop
  5. Amiga A500
  6. Technical reference manual

Commodore Amiga A500 Technical Reference Manual

Hide thumbs Also See for Amiga A500:
Table of Contents

Advertisement

Quick Links

See also: Technical Reference Manual
Commodore
Amiga
®
®
A500/A2000
Technical Reference
Manual

Advertisement

Table of Contents
loading

Related Manuals for Commodore Amiga A500

Summary of Contents for Commodore Amiga A500

  • Page 1 Commodore Amiga ® ® A500/A2000 Technical Reference Manual...
  • Page 2 COPYRIGHT This manual is copyright © 1986,1987 by Commodore-Amiga, Inc. All Rights Reserved. This document may not, in whole or part, be copied, photocopied, reproduced, translated or transferred to any electronic medium or machine readable form without prior consent, in writing, from Commodore-Amiga, Inc.

  • Page 3: Table Of Contents

    A2000/A500 Technical Reference Manual Table of Contents Section 1 Summary of Differences Section 2 System Block Diagrams Section 3 Amiga Expansion Designing hardware Amiga Expansion Architecture Driver Documentation Software for Amiga Expansion Amiga Expansion Connectors 100 Pin 86 Pin Video Slot Section 4 PC Bridgeboard Description of the PC/XT emulator for the Amiga 2000...

  • Page 4: Section 1 Summary Of Differences

    This manual presents technical documentation for three different Amiga models, comparing them to the original Amiga, referred to as model A1000. Technical information included in this manual is rel- evant for the following Commodore Amiga models: ● the Amiga 500 (A500), a low-cost version of the origi- nal Amiga computer, software-compatible with the A1000.

  • Page 5: The Keyboard

    Print screen (asterisk) and Scroll lock (right parenthesis). On some keyboards, the left Amiga key has been replaced by the Commodore key. This key performs identically in either case. RAW KEY CODES ON Keyboard Layout Showing Raw Key Codes THE KEYBOARD Figure 1.1 Key Codes...
  • Page 6 RS232 and MIDI Port The RS232 connector on the A500 and A2000 is form fit and function identical to a Commodore PC-10/20 with a few exceptions. This is the OPPOSITE sex connector from the A1000. The connector is a shielded male DB25P connector. The A1000 supplies various non-standard RS232 signals on the DB25 connector.
  • Page 7 As you will notice, the A500 and 2000 deletes clocks and interrupt lines from the A1000. The +/-5Vdc and reset lines are also deleted. The +/- 12Vdc lines are identical to a PC10/20. The following signals (formerly on the RS232 connector) can be found on other connectors: ResB = parallel connector C2 = video connector...
  • Page 8 stead of the A1000. An A500 genlock will also have to supply its own power. Power will not be provided for the Genlock. All signals on the 23 pin connector are the same except for the power. In addition to the 23 pin video connector, the A500/B2000 provides a monochrome composite video output, unlike the A1000.
  • Page 9 The 23 pin D-type connector with sockets (DB23S) at the rear of the External Disk Interface Amiga is nominally used to interface to MFM devices. Connector The second disk drive port is similar to the A1000, and is therefore compatible with the 1010 or the 1020 disk drive. The CPU will power one external 1010 disk drive.
  • Page 10 TKO* Asserted by selected drive when read/write head is positioned over track 0. DKWEB* Write gate (enable) to drive. DKWDB* MFM output data from Amiga. STEPB* Selected drive steps one cylinder in the direction indicated by DIRB. DIRB Direction to step the head. Inactive to step towards center of disk (higher numbered tracks).
  • Page 11 $FFFF FFFF - Amiga standard 3.25 diskette $5555 5555 - 48 TPI double density double sided As with other peripheral ID's, users should con- tact Commodore Technical Support for ID Assignment. The serial input data is active low and must there- fore be inverted to be consistent with the above table.
  • Page 12 15 KHz will be required for most applications. This permits wider frequency response by using faster sampling rates. A500 Reset The A500 implements a "hard-wired" Control/Commodore/Amiga key reset rather than the "soft" A1000/A2000 keyboard reset. "Shut down" keyboard messages are not transmitted.
  • Page 13 Table 1 -1 RAW KEY CODES Unshifted Shifted Raw Key Default Default Number Keycap Legend Value Value ‘ ~ ' (Accent grave) ~ (tilde) 7& & - (Hyphen) _ (Underscore) \ │ │ (undefined) 0 (Numeric pad) (undefined) 1 (Numeric pad) 2 (Numeric pad) 3 (Numeric pad) ‘...
  • Page 14 Unshifted Shifted Keycap Default Default Number Legend Value Value (RESERVED) (RESERVED) (undefined) 4 (Numeric pad) 5 (Numeric pad) 6 (Numeric pad) (RESERVED) (RESERVED) , < , (comma) < . > . (period) > (undefined) . (Numeric pad) 7 (Numeric pad) 8 (Numeric pad) 9 (Numeric pad) (Space bar)
  • Page 15 Unshifted Shifted Keycap Default Default Number Legend Value Value <CSI>0~ <CSI>10~ <CSI>1~ <CSI>11~ <CSI>2~ <CSI>12~ <CSI>3~ <CSI>13~ <CSI>4~ <CSI>14~ <CSI>5~ <CSI>15~ <CSI>6~ <CSI>16~ <CSI>7~ <CSI>17~ <CSI>8~ <CSI>18~ <CSI>9~ <CSI>19~ HELP <CSI>?~ <CSI>?~...

  • Page 16: System Block Diagrams

    Section 2 System Block Diagrams This section features system block diagrams for each new Amiga, INTRODUCTION the A2000, B2000 and A500, in that order.
  • Page 18 62 pin PC - Connector 36 pin Conn. 100 pin AMIGA - Connector 62 pin PC - Connector 36 pin Conn. 100 pin AMIGA - Connector 86 pin MMU - Connector VIDEO MOD.
  • Page 20 Section 3.1 Designing Hardware for the Amiga Expansion Architecture This section gives guidelines for designing hardware to reside on the INTRODUCTION Amiga expansion bus. The Amiga expansion bus is a relatively straightforward extension of the 68000 bus. Hardware for the bus can be viewed as two categories: backplanes and PICs.
  • Page 21 As shown in Figure 3.1, "Expansion Architecture Overview," the ex- EXPANSION pansion bus is implemented as backplane (an expansion box) which ARCHITECTURE accept PICs (boards). The recommended number of PICs to a back- OVERVIEW plane is five. Due to timing considerations, it is not possible to daisy-chain more than two buffered backplanes without inserting wait states.
  • Page 22 Active Active high signals are considered active when they are in GLOSSARY the "one state" or "high state". Active low signals are considered ac- tive when they are "low" or in the “zero state”. Active high signals do not have barred signal names. Active low signals do have barred signal names.

  • Page 23: Design Guidelines

    DESIGN GUIDELINES FOR BACKPLANES Collision Detection In this context, collisions are defined as any instance of two slaves Circuit attempting to respond to the same bus cycle. All backplanes must have a collision detect circuit. The reason is that the PICs are auto-configurable and can be accidently instructed by software to respond to overlapping address spaces.
  • Page 24 The buffer control logic controls output enable and direction of the Buffer Control Logic bidirectional tri-state bus drivers. See the STEERING PAL equation. Table 3-2. Data Driver Timing It should be noted that the backplane drivers must not turn on until the rise of S4 during a read.
  • Page 25 A PIC as master must drive the bus using the same protocol as the Read or Write Cycle 68000. Some of the timing margins must be better than those from with a PIC as Master the 68000, because the PIC is driving through several levels of buff- ers, and the Amiga logic is designed to the 68000 (8 megahertz part) specs.
  • Page 26 Interrupt latency on the Amiga is highly INTERRUPT LATENCY-- application software dependent, this is -BLITTER, MASKED INTS because the Blitter can be operated in "nasty mode" at the software's option. If the blitter is "nasty" and is given a lot of work to do.
  • Page 27 1) The loading, buffering and layout requirements specified for the Expansion Notes A1000/A500 expansion connector must be strictly followed for reliable operation. Unbuffered devices and bus line extension are known problem areas. 2) Unbuffered daisy-chaining of multiple external expansion devices is not supported.
  • Page 28 DESIGN GUIDELINES FOR PICs All PICs implement the auto-configuration protocol. The auto config Auto Configuration protocol is designed so that system auto-config software can inter- rogate the PICs ID locations, build a system table of the installed PICs, and place the PICs in the 68000 memory space. General Description of If it is difficult to imagine how to implement this protocol while it's being described, don't worry.
  • Page 29 requirement is because the eight megabyte space reserved for ex- pansion in the current machine begins at hex 200000 (See auto-con- fig notes below). Auto-Config Notes 1)There is currently no provision for 6MB PICs. Designers of 8 MB memory boards should consider auto-configs as two PICs to al low partial loading flexibility.
  • Page 30 (04/06) Product number, this number is defined by the manufacturer of the board and is used by auto- config software to initialize drivers for the board. 7 6 5 4 (08/OA) Reserved, must be as specified Bits are currently zero 0 means this board can be shut up 1 means this board cannot be shut up 0 means any space okay...
  • Page 31 (40/42) Optional control status register 7 6 5 4 Write Read Interrupt enable Interrupt enable User definable don't care Local reset must be 0 User definable don't care User definable INT2 pending User definable INT6 pending User definable INT7 pending User definable I am pulling INT (44/46)
  • Page 32 We have designed a backplane as an example implementation of our EXAMPLE BACKPLANE expansion architecture. This section is a detailed description of the DESIGN schematic of that backplane. The schematic appears as Figure A-1 in Appendix A. Backplane Schematic While reading this section, refer to the backplane schematics for the A2000 and PALS to see what is being described.
  • Page 33 DMAIN is active when the bus master is upstream from this back- plane. So when DMAIN is active. DMAOUT must go active. OWN* is the wire OR'ed signal which means that this backplane has the current bus master. Thus, because all PICs on this backplane are upstream from the address (and data) buffers, DMAOUT must be active when OWN (or OWN*) is active.
  • Page 34 It is fairly difficult to avoid tri-state fights on the data buffers. In or- der to get data out to dynamic RAM PICs at an early enough time, we do not use the data strobes to enable the data drivers, because these strobes can go active very late in a write cycle.
  • Page 35 The collision circuit also monitors A23 through A19 and OVR* on the bus, so that the internal reserved address spaces of the Amiga can be checked. An access to any of the internal address spaces will make the Amiga respond as the slave unless OVR* (override) is asserted.
  • Page 36 By the way, don't worry about two slaves colliding on the upstream of the backplane; that backplane has a collision detect circuit of its own. Thus, each of the seven product terms indicates that a collision is not happening at this time. Only one of them needs to be true to know that a collision is not happening at this time.
  • Page 37 Clock Buffers BACKPLANE TIMING GENERATION The clock buffers for C1 *, C3*, and CDAC were chosen for minimum propagation delay and minimum skew. Notice that buffered clocks are passed to the 100 pin edge connectors, but that the unbuffered clocks are passed to the 86 pin connector that goes on to the next box in order to minimize propagation delay to the next backplane.
  • Page 38 This section is a description of the schematic for a small 16 kilobyte EXAMPLE PIC DESIGN RAM board that we designed as our first test PIC for the expansion architecture. The schematic for this board is Figure A.2, in Appendix A, It is valuable as an example because it implements all of the basic features of a slave PIC.
  • Page 39 Further analysis of the BD15-BD12 equations will show that almost all addresses put out ones; however, remember that most of the nibbles are inverted because the spec says they have to be. The inversion makes it possible to implement the codes in active low PALs;...
  • Page 40 14/16 0000 0000 = Low byte of manufacturer's number 40/42 0000 0000 = Because this PIC does not generate INTs When you want to program your own ID PAL, just work back to the equations. First determine what ID pattern you need by reading about the nibbles in the spec.
  • Page 41 Timing Requirements for PIC TIMING REQUIREMENTS FOR PIC AS SLAVE (RD & WR CYCLES) Characteristic Unit AS* low to SLAVE* Low AS* high to SLAVE* high AS* low to XRDY low (to insert wait) Read Data Valid to local 7M low (S7) AS* low to OVR* low AS* high to OVR* high TIMING REQUIREMENTS FOR PIC AS MASTER (RD &...
  • Page 42 The following numbers and notations are used for standard load and 2000 SYSTEM BUS drive values: LOADING From A2000 To A2000 Type (IC input load) (IC output drive) F-Driver TTL 2.0V @ -15mA 20μA @ 2.7V 0.5V @ 64mA -1.6mA @ 0.5V F-Series TTL 2.7V @ -1mA A @ 2.7V...
  • Page 43 Named Expansion Coprocessor Video Signals Slots (each) Slot Slot /EINT7 /SLAVEn /CFGOUTn /COPCFG E Clock 7MHz Clock /BERR /VPA /VMA /RST /HLT /OWN /BRn /CBR /CBG /BGACK /BOSS XCLK /XCLKEN...
  • Page 44 TABLE 3-2 PAL16L8 STEERING150R17REV3 11-17-85 AMIGA /SLVOUT RD /ASQ /ASQ90 COLLIS /BG /AS /BGACK /DMAIN GND /OWN /AOE /UDS /BERR /DMAOUT /LDS /DBOE /RES /D2P VCC DBOE = AS * /RD * /BERR + ;DATA DRIVERS DURING WRITE CYCLE UDS * RD * ASQ * /BERR + ;TURN ON DRIVERS LATE FOR RD LDS* RD* ASQ* /BERR UDS AND LDS PROTECT RD MOD WR...
  • Page 45 TABLE 3-3 PAL16R6 ARBITRATE REV1 1-6-86 AMIGA 7M /BRIN /RES /BGiN /BR5 /BR4 /BR3 /BR2 /BR1 GND GROUND /BGOUT /BGOLD /BG5 /BG4 /BG3 /BG2 /BG1 /BR VCC BG1 = BGIN * /BGOLD * BR1 * /RES + GENERATE BG1 BGIN * BG1 /RES ;HOLD UNTIL /BG BG2 = BGIN * /BGOLD •...
  • Page 46 TABLE 3-4 PAL20L10 TESTRAM 9-11-85 COMMODORE-AMIGA /ASQ /ASQQ RD /BDSEL /BERR A6 A5 A4 A3 A2 A1 GND/RES BD12 BD13 BD14 BD15/PRECON /CONOUT /SHUTUP /RAMOE /WP /DBOE VCC DBOE = /RES*BDSEL*/BERR*/SHUTUP*/RD + ;WRITES TURN ON EARLY /RES*BDSEL*/BERR*SHUTUP* RD*ASQ ;ASQ DELAYS THE READ...
  • Page 47 TABLE 3-5 PAL16L8 COLLISION 11-17-8S AMIGA /BAS /SLV1 /SLV2 /SLV3 /SLV4 /SLV5 /SLVIN A23 A22 GND A21 /SLVOUT A20 A19 /OVR /RESET P17 /PROC /NOTCOLIS VCC SLVOUT = SLV1 + SLV2 + SLV3 + SLV4 + SLV5 + SLVIN NOTCOLIS = /SLV1 * /SLV2 * /SLV3 * /SLV4 * /SLV5 * /SLVIN + /PROC * /SLV2 * /SLV3 * /SLV4 * /SLV5 * /SLVIN +...
  • Page 48 This section gives the necessary information for interfacing to the INTERFACING TO THE 68000 bus connector on the left side of the Amiga A500 (or the 68K BUS CONNECTOR right side of the A1000). ON THE AMIGA 500 THE CONNECTOR ON THE AMIGA The connector is a standard dual row 86 finger (43 on a side) edge connector, spaced on .1"...
  • Page 49 If you need a 14.31818Mhz synchronous clock, you can generate it (7Mequiv) XOR (CDAC) = 14M equivalent S y n c d S 2 ~139ns CDAC 1 s t Q r t l C1∗ C3∗ Fig. 3.2 Amiga System Clocks The 68000 is connected directly to the 86 pin connector, there are Bus Timing no buffers between the 68000 and the connector.
  • Page 50 CPU bus timing is based on an 8Mhz 68000, with only one excep- tion: under normal operation, the bus control PAL asserts DTACK* for you. DO NOT ASSERT DTACK*; do not attach any outputs to the DTACK* line. Slave Bus Timing Details of 68000 timing are available in the Motorola 68000 hard- ware manual.
  • Page 51 7M = CLK XXXXXXX XXXX A23-A1 UDS ,LDS* XXXXXX XXXX D15-D0 DTACK* Fig. 3.3 Standard 4 Clock Read Cycle 7M = CLK XXXXXXX XXXX A23-A1 UDS ,LDS* XXXXX D15-D0 DTACK* Fig. 3.4 Standard 4 Clock Write Cycle...
  • Page 52 7M = CLK XXXX XXXXXXX A23-A1 AS∗ XRDY 60ns max DTACK∗ XXXX D15-D0 Fig. 3.5 Using XRDY to Delay DTACK* All bus masters must run synchronously to 7M (equivalent), as does Master Bus Timing the 68000 in the Amiga. The necessary information for designing a bus master is in the 68000 hardware manual.
  • Page 54 Section 3.2 Driver documentation This section discusses how the "binddrivers" program finds your driver and links it into the system. It also hints on how to write your code to take advantage of this. First off. the expansion library goes out and configures the expan- sion boards in the system.
  • Page 55 6. InitResident () the loaded code. If an error (NULL) is returned, UnLoadSeg () the segment your driver code: Find the list of boards. Mark them a configured, and record your driver in them (for system debugging). Return non-zero value if everything went ok. If something went wrong (or you just want to be unloaded) then return NULL.
  • Page 56 This is why we refer to loading a "driver'" rather than a "device" — you can write any sort of code you want to handle your device. 5. Binddriver will search the first hunk for a Resident structure. If it cannot find one, it will assume some awful mistake has been made, and will unload the segment 6.

  • Page 58: Software For Amiga Expansion

    Section 3.3 Software for Amiga Expansion This section contains listings and information on the following expansion software commands: expansion.library/AddDosNode expansion.library/MakeDosNode System/Libraries/Expansion/AddConfigDev System/Libraries/Expansion/AllocBoardMem System/Libraries/Expansion/AUocConfigDev System/Libraries/Expansion/AllocExpansionMem System/Libraries/Expansion/ConfigBoard System/Libraries/Expansion/ConfigChain System/Libraries/Expansion/FindConfigDev System/Libraries/Expansion/FreeBoardMem System/Libraries/Expansion/FreeConfigDev System/Libraries/Expansion/FreeExpansionMem System/Libraries/Expansion/GetCurrentBinding System/Libraries/Expansion/ObtainConfigBinding System/Libraries/Expansion/ReadExpansionByte System/Libraries/Expansion/ReadExpansionRom System/Libraries/Expansion/ReleaseConfigBinding System/Libraries/Expansion/RemConfigDev System/Libraries/Expansion/SetCurrentBinding System/Libraries/ExpansionA/VriteExpansionByte NAME EXPANSION.LIBRARY/ ADDDOSNODE AddDosNode —...
  • Page 59 We hope to eventually try and boot off a disk device. We will try and boot off of each device in turn, based on priority, if there is no boot floppy in the floppy disk drive. As of this writing that facility does not yet exist.
  • Page 60 EXAMPLES /* enter a bootable disk into the system. Start a file handler ** process immediately. AddDosNode( 0, ADNF_STARTPROC, MakeDosNode( paramPacket) BUGS The flexible boot strategy is only that — strategy. It still needs to be reflected in code somewhere. SEE ALSO MakeDosNode EXPANSI0N.LIBRARY/...
  • Page 61 longword description string with dos handler name string with exec device name unit number (for OpenDevice) flags (for OpenDevice) # of longwords in rest of environment file handler environment (see libraries/file- handler.h) RESULTS deviceNode — pointer to initialize device node structure, or null if there was not enough memory.
  • Page 62 NAME SYSTEM/LIBRARIES/ EXPANSION/ AddConfigDev — add a new ConfigDev structure to the system ADDCONFIGDEV SYNOPSIS AddConfigDev( configDev) FUNCTION This routine adds the specified ConfigDev structure to the list of Configuration Devices in the system. INPUTS configDev — a valid ConfigDev structure. RESULTS EXCEPTIONS SEE ALSO...
  • Page 63 INPUTS slotSpec — the memory size field of the Type byte of an expansion board RESULTS startSlot — the slot number that was allocated, or -1 for error. EXAMPLES struct ExpansionRom *er; slot = AllocBoardMemf er->er_Type & ERT_MEMMASK ) EXCEPTIONS SEE ALSO AllocExpansionMem.
  • Page 64 SEE ALSO FreeConfigDev BUGS SYSTEM/LIBRARIES/ NAME EXPANSION/ AllocExpansionMem — allocate expansion memory ALLOCEXPANSIONMEM SYNOPSIS startSlot = AllocExpansionMem( numSlots. slotOffset) FUNCTION This function allocates numslots of expansion space (each slot is E_SLOTSIZE bytes). It returns the slot number of the start of the expansion memory.
  • Page 65 EXAMPLES AllocExpansionMem( 2,0) Tries to allocate 2 slots on a two slot boundary. AllocExpansionMem( 64, 32) This is the allocation rule for 4 meg boards. It allocates 4 megabytes (64 slots) on an odd 2 meg boundary. EXCEPTIONS SEE ALSO FreeExpansionMem, AllocBoardMem, FreeBoardMem BUGS NAME...
  • Page 66 EXCEPTIONS SEE ALSO FreeConfigDev BUGS SYSTEM/LIBRARIES/ NAME EXPANSION/ ConfigChain — configure the whole damn system CONFIGCHAIN SYNOPSIS error = ConfigChain( baseAddr) FUNCTION This is the big one! This routine will take a base address (generally E_EXPANSIONBASE) and configure all the devices that live there. This routine will call all the other routines that might need to be called.
  • Page 67 NAME SYSTEM/LIBRARIES/ EXPANSION/ FindConfigDev — find a matching ConfigDev entry FINDCONFIGDEV SYNOPSIS configDev = FindConfigDev( oldConfigDev. manufacturer, product) FUNCTION This routine searches the list of existing ConfigDev structures in the system and looks for one that has the specified manufacturer and product codes.
  • Page 68 NAME SYSTEM/LIBRARIES/ EXPANSION/ FreeBoardMem — allocate standard device expansion memory FREEBOARDMEM SYNOPSIS FreeBoardMem( startSlot. SlotSpec ) FUNCTION This function frees numslots of expansion space (each slot is E_SLOTSIZE bytes)- It is the inverse function of AllocBoardMem(). INPUTS startSlot — a slot number in expansion space. slotSpec —...
  • Page 69 NAME SYSTEM/LIBRARIES/ EXPANSION/ FreeConfigDev — allocate a ConfigDev structure FREECONFIGDEV SYNOPSIS FreeConfigDev(configDev) FUNCTION This routine frees a ConfigDev structure as returned by AllocConfigDev. INPUTS configDev — a valid ConfigDev structure. RESULTS EXCEPTIONS SEE ALSO AllocConfigDev BUGS SYSTEM/LIBRARIES/ NAME EXPANSION/ FreeExpansionMem — allocate standard device expansion memory FREEEXPANSIONMEM SYNOPSIS FreeExpansionMem(startSlot, numSlots)
  • Page 70 EXAMPLES EXCEPTIONS If the caller tries to free a slot that is already in the free list, FreeExpansionMem will Alert() (e.g. crash the system). SEE ALSO AllocExpansionMem, AllocBoardMem, FreeBoardMem BUGS SYSTEM/LIBRARIES/ NAME EXPANSION/ GetCurrentBinding — sets static board configuration area GETCURRENTBINDING SYNOPSIS actual = GetCurrentBinding( currentBinding, size)
  • Page 71 RESULTS actual — the true size of a CurrentBinding structure is returned. EXAMPLES EXCEPTIONS SEE ALSO GetCurrentBinding BUGS SYSTEM/LIBRARIES/ NAME EXPANSION/ ObtainConfigBinding — try to get permission to bind drivers OBTAINCONFIGBINDIN SYNOPSIS ObtainConfigBinding() FUNCTION ObtainConfigBinding gives permission to bind drivers to ConfigDev structures.
  • Page 72 BUGS SYSTEM/LIBRARIES/ NAME EXPANSION/ ReadExpansionByte read a byte nybble by nybble. READEXPANSIONBYTE SYNOPSIS byte = ReadExpansionByte( board, offset ) FUNCTION ReadExpansionByte reads a byte from a new-style expansion board. These boards have their readable data organized as a series of nybbles in memory.
  • Page 73 NAME SYSTEM/LIBRARIES/ EXPANSION/ ReadExpansionRom— read a board's configuration ROM space READEXPANSIONROM SYNOPSIS error = ReadExpansionRom( board, configDev ) FUNCTION ReadExpansionRom reads a the ROM portion of an expansion device in to cd_Rom portion of a ConfigDev structure. This routine knows how to detect whether or not there is actually a board there, In addition, the Rom portion of a new style expansion board is en- coded in ones-complement format (except for the first two nybbles...
  • Page 74 NAME SYSTEM/LIBRARIES/ EXPANSION/RELEASE ReleaseConfigBinding — allow others to bind to drivers CONFIGBINDING SYNOPSIS ReleaseConfigBinding() FUNCTION This call should be used when you are done binding drivers to ConfigDev entries. It releases the SignalSemaphore; this allows others to bind their drivers to ConfigDev structures. INPUTS RESULTS EXAMPLES...
  • Page 75 EXCEPTIONS SEE ALSO AddConfigDev BUGS SYSTEM/LIBRARIES/ NAME EXPANSION/ SetCurrentBinding —- sets static board configuration area SETCURRENTBINDING SYNOPSIS SetCurrentBinding( currentBinding. size ) DO: 16 FUNCTION This function records the contents of the "CurrentBinding" structure in a private place. It may be read via GetCurrentBinding( ). This is really a kludge, but it is the only way to pass extra arguments to a newly configured device.
  • Page 76 SEE ALSO GetCurrentBinding BUGS SYSTEM/LIBRARIES/ NAME EXPANSION/ e a byte nybble by nybble. WriteExpansionByte — writ WRITEEXPANSIONBYTE SYNOPSIS error = WriteExpansionByte( board, offset, byte ) FUNCTION WriteExpansionByte write a byte to a new-style expansion board. These boards have their writeable data organized as a series of nyb- bles in memory.
  • Page 77 EXAMPLES err - WriteExpansionByte(cd->BoardAddr, ECOFFSET (ec_Shutup),O); err = WriteExpansionByte( cd->BoardAddr, ECOFFSET ( ec_Interrupt). 1 ); EXCEPTIONS SEE ALSO ReadExpansionByte, ReadExpansionRom BUGS...
  • Page 78 Most of the Expansion Bus signals are buffered (the ZORRO detail will of course depend on the design; the characteristics assumed here will be present if the Commodore-Amiga design specifications are followed). This is an important point to keep in mind, for...
  • Page 79 tween all Expansion Slots. The terms 86 Pin Slot Coprocessor Slot, and Local Slot are considered synonyms, and pertain to the 86 pin Coprocessor Slot in the A2000 and B2000. The terms 86 Pin Edge and Expansion Edge are considered synonyms, and pertain to'the 86 pin Expansion Edge in the A1000 and A500.
  • Page 80 Higher voltage supply, useful for communications cards and other High Voltage Supply devices requiring greater than digital voltage levels. This is intended ( + 12V) for small loading only; there's a total of 8 Amps for the entire A2000 system, much of which is normally devoted to floppy and hard disk drive motors.
  • Page 81 This is the 7.16 MHz system clock. On A2000/B2000 design has 7MHZ Clock true 7MHz which is actually in common with the 68000's 7MHz in- put On the original ZORRO bus specification this was the EQU7MHZ signal, a 7M equivalent made using the relationship EQU7MHz = /C1 XNOR /C3.
  • Page 82 These are buffered versions of the 68000's upper and lower data Data Strobes (/LDS, strobes. The strobes fall on data valid during transfer; the lower /UDS) strobe being used for the lower byte (even byte address), the upper strobe being used for the upper byte (odd byte address). These are considered by the data bus buffers during read cycles, in case the cy- cle actually turns out to be a read-modify-write cycle.
  • Page 83 This is an input that goes directly to the 68000. It is used to indicate Bus Error (/BERR) the occurrence of some kind of bus error. Any expansion card capa- ble of detecting a bus error relating directly to that card can assert /BERR when that bus error condition is detected.
  • Page 84 bus also provides the encoded interrupt lines /IPL0. /1PL1, and /IPL2 on bus pins 40.42, and 44 respectively. These are useless as inputs, but as outputs are required by any Coprocessor or alternate proces- sor that needs to monitor system interrupts. In the A2000/B2000 scheme, coprocessors sit in the Coprocessor Slot which allows them full control of the system.
  • Page 85 This group of signals is responsible for the control of things that SLOT CONTROL happen between Expansion Slots. SIGNALS Pin 9 is the SLAVEn signal, where "n" refers to the Expansion Slot Slave (/SLAVEn) number. Each Slot has its own SLAVE output, all of which go into the collision detect circuitry.
  • Page 86 Asserted by Expansion Bus DMA device when it becomes bus master. PIC is DMA Owner This output is to be treated as a wired-OR output between all (/OWN) Expansion Slots, any of which may have a PIC signalling bus mastership. Thus, this should be driven with an open-collector or similar output by any PIC using it Found on pin 7.
  • Page 87 There are three instances of the Expansion Bus (so far), the original 100 PIN CONNECTOR A1000/ZORR0 specification, and the A2000 enhancement to this PINOUTS original spec, and the B2000 (A2000-CR) specification. The ZORRO specification is treated as a single instance for the purposes of this chart, even though there are several different ZORRO bus implementations from several different hardware manufacturers.
  • Page 88 PIN ZORRO A2000 B2000 Buffered? Function /IPL1 /EINT5 /IPL2 /E1NT4 /BEER /VPA Ground E Clock A/MA /RST /HLT /BRn Ground /BGACK /BGn /DTACK READ /LDS /UDS Ground Ground Ground Ground...
  • Page 89 PIN ZORRO B2000 A2000 Buffered Function Ground Ground Ground EQU7MHZ 7MHz /BUSRST /GBG No Connect /EINT1 No Connect No Connect Ground Ground...
  • Page 90 Coprocessor Expansion and 86 Pin Signals This section details the signals found on the various types of 86 pin INTRODUCTION expansion connectors on different Amiga computers, especially the signals found on the B2000 computer's 86 pin Coprocessor Slot, and how these differ from the similar signals found on A2000 computers and those of the original A1000 computers.
  • Page 91 The Coprocessor Slot signals discussed below apply for most of the COPROCESSOR SLOT machines, though in some cases the item mentioned exists on only SIGNALS some of the machines; these are specified. Most of these signals are directly in common with the 68000. or directly a part of the 68000 local bus.
  • Page 92 There are various system clocks available at all Local Bus Ports, use- CLOCK SIGNALS ful in designing synchronous Coprocessor systems. Loading on these clocks should be watched very carefully on all types of Amiga com- puters. /C1 Clock This is a 3.58 MHz clock synched to the falling edge of the 7.16 MHz system clock.
  • Page 93 These signals are various items used for the addressing of resources ADDRESSING AND on a coprocessor card by the 68000 and any DMA devices, and for CONTROL SIGNALS 24 by 16 bit addressing of other system resources by a coprocessor device (which may easily have more potential).
  • Page 94 These are the 68000's upper and lower data strobes. The strobes Data Strobes (/LDS, fall on data valid during transfer; the lower strobe being used for /UDS) the lower byte (even byte address), the upper strobe being used for the upper byte (odd byte address). Like /AS, these must be driven by the Coprocessor as it assumes control, as the 68000 pins will tri- state.
  • Page 95 These signals are the 68000 Processor Status outputs, which can be Processor Status used by bus devices to determine the internal state of the 68000 (FC0-FC2) any time /AS is asserted. When a coprocessor is in charge, it must drive these pins in a way compatible with how the 68000 does it. The different 68000 status codes can be found in any 68000 spec sheet.
  • Page 96 Two of the 68000 non-encoded interrupt inputs are available at the Decoded Interrupts Coprocessor slot, on pin 19 for interrupt level 2 (/INT2) and on pin 22 for interrupt level 6 (/INT6). These are the same interrupts used by the Amiga internal system chips and encoded by the Paula chip. They can be used by a Coprocessor board by driving them to gener- ate 68000 interrupts when the 68000 is in charge, though generally they don't do much when the Coprocessor is in charge.
  • Page 97 External Ready (XRDY) This input provides a way for an external device to delay the motherboard generated /DTACK, for things like slow memory and I/O boards that need to add wait states. This signal should be negated very quickly, no later than 60ns from address valid (/AS asserted), in order for the motherboard circuitry to have enough time to prevent the normal assertion of /DTACK.
  • Page 98 All instances of Local Expansion Ports have a Bus Request to 68000 BUS Request (/BR,/CBR) of some kind. In the A2000. as in the A500 and A1000, this is directly connected to the 68000's /BR input, which is considered a wired-OR input;...
  • Page 99 The B2000 computer implements an extended version of the THE B2000 A2000's Coprocessor Slot, designed to make the swapping of main COPROCESSOR processors under program control much more powerful and trans- INTERFACE parent to the rest of the B2000 system. There are things that can be done from the B2000 Coprocessor slot that can't be done from the A2000's Coprocessor Slot, so this is an important consideration to anyone designing a Coprocessor device of some kind.
  • Page 100 The B2000 Coprocessor The B2000 hardware has implemented a more sophisticated Co- Solution processor system that removes these problems. The B2000 Co- processor Slot has a signal called /CBR (Coprocessor Bus Request) as a replacement for /BR, a signal called /CBG {Coprocessor Bus Grant) as a replacement for /BG, and one additional signal, /BOSS, which is also known as Coprocessor Grant Acknowledge.
  • Page 101 86 PIN CONNECTOR Here are the four instances of the 86 pin Local Bus, the A500 and PINOUTS A1000 Edge connectors, used for all kinds of expansion on those machines, and the A2000 and B2000 Coprocessor slots. PIN A500 A10O0 A2000 B2000 Function Ground Ground Ground...
  • Page 102 A500 A1000 A2000 B2000 Function /IPLO /IPL1 /IPL2 /BEER A/PA Ground E Clock /VMA /RST /HLT /CBR Ground /BGACK /CBG /DTACK /LDS /UDS Ground...
  • Page 103 A500 A1000 A2000 B2000 Function Ground...

  • Page 104: Video Slot

    The Amiga 2000 Video Slot This document details the signals found on the internal video slot of INTRODUCTION the Amiga 2000 (A2000), and the additional component of this slot as implemented on the B2000 model. The A2000 video connector is a 36 pin edge connector, mechanically similar to the slot extension connector of an IBM PC-AT.
  • Page 105 Found, respectively, on pins 7,11, and Digital Video These signals serve as digital output, suitable for use with an IBM or Commodore 128 style 4 bit digital color or monochrome monitor or similar output device. On the B2000, these (in conjunction with...
  • Page 106 other signals found on the second video connector) provide access to the full 12 bits of digital video output produced on the motherboard by the Denise chip (4 bits each of R, G, and B). Each of these outputs is 47 Ohm terminated. The pin assignments are Digital Red (R3) on pin 29, Digital Green (G3) on pin 27, Digital Blue (B3) on pin 25, and Digital Intensity (BO) on pin 23.
  • Page 107 The Extended Video Slot provides several different voltages designed POWER CONNECTIONS to supply Video devices. The A2000 power supply is currently rated at 200 Watts, which supplies the main board and all other expansion ports as well as the Video Slot. Digital/Video Ground These pins provide additional grounding for digital or video based devices.
  • Page 108 The remaining 8 bits of digital video are available on this connector. Digital Video The signals are Red 0-2 {pins 2. 3. 4). Green 0-2 (pins 6. 7, 8), and Blue 1 -2 (pins 10 and 11). The timing of the digital video is not tightly specified.
  • Page 109 The B2000 Extended Video Slot offers a few additional audio sig- AUDIO SIGNALS nals. Raw Audio These are the left and right audio channels before they're passed through the low pass filter on output For many applications, the audio sampling rate is low, and as such requires a low pass filter to be in place at fc = 6 kHz or so, to prevent audio aliasing.
  • Page 110 The expanded B2000 video slot is a 36 pin edge connector, the same type as used on the 16 bit IBM style bus extension. Signal Signal Ground Ground Ground Ground Composite Video TBASE CDAC Clock POUT /C3 Clock BUSY /LPEN /ACK Ground /LED...
  • Page 112 Section 4.1 Description of PC/XT Emulator for AMIGA 2000 AMIGA ACCESS: Amiga Interface Offset Address = Base Addr. Base Addr. + (00000 - 1FFFF) : Byte Access Base Addr. + (20000 - 3FFFF) : Word Access Base Addr. + (40000 - 5FFFF) : Graphic Access Base Addr.
  • Page 113 PC MEMORY AND I/O MAP: kind of Amiga Interface PC Address Range Size Usage access Offset Address 0000 ... 03FF IO-PAGE 1E000 ... 1FFFF 3E000 ... 3FFFF 5E000 ... 5FFFF 7E000 ... 7FFFF AOOOO ... AFFFF DISK BUFFER RAM (*) 00000 ..
  • Page 114 40000 ... 4FFFF D0000 ... DFFFF DISK BUFFER RAM (*) 40000 ... 4FFFF E0000 ... EFFFF DISK BUFFER RAM (*) 50000 ... 57FFF B8000 ... BFFFF COLOR VIDEO RAM 58000 ... 5BFFF F0000 ... F3FFF PARAMETER RAM 5C000 ... 5DFFF B0000 ...
  • Page 115 AMIGA MEMORY MAP: Amiga Interface kind of Offset Address PC Address Range Size Usage access 24000 ... 2FFFF D4000 ... DFFFF DISK BUFFER RAM (*) 30000 ... 37FFF B8000 ... BFFFF COLOR VIDEO RAM 38000 ... 3BFFF D0000 ... D3FFF PARAMETER RAM 3C000 ...
  • Page 116 PC/AT I/O Offset Address Address Usage INTERFACE: / AMIGA " RESET IRQ7 1E1BF 7E1BF " INTERRUPT CONTROL 1E19F 7E19F BIT 6 = 0 : ON BIT6 = 0:OFF " CONTROL 1E1DF 7E1DF " CONTROL 1E19F 7E19F MONO CRT ADDRESS INDEX REGISTER 1E1FF 7E1FF "...
  • Page 117 PC/AT I/O Offset Address Address Usage INTERFACE: / AMIGA DUMMY (R/W) 1E01F 7E01F PC/AT I/O Offset Address Address Usage INTERFACE: / AMIGA COLOR CRT ADDRESS INDEX REGISTER 1E21F 7E21F DUMMY 1E01F 7E01F " CRT ADDRESS INDEX REGISTER 1E21F 7E21F DUMMY 1E01F 7E01F "...

  • Page 118: Register Description

    AMIGA I/O MEMORY MAP (REGISTER DESCRIPTION) Offset Address AMIGA Register Interface / Memory INTERFACE: / AMIGA AMIGA INTERRUPT STATUS read register 1FF1 7FF1 INTERRUPT STATUS read register 1FFF3 7FFF3 NEGATE PC RESET read register 1FFF5 7FFF5 MODE REGISTER read register / write register 1FFF7 7FFF7...
  • Page 119 Negation HOW to Clear an |RQ3_a Read to i/o location 3bO hex Asserted Interrupt IRQ3_b Read com2 register 2F8 hex Signal IRQ7 Read line printer status register 379 hex AMIGA SIDE All registers on the memory locations 1FFFO TO 1FFFF are only accessable from the AMIGA side.
  • Page 120 A read access to this register negates the PC reset line and allows Negate PC Reset (R) the PC to start the boot procedure. On power-on the PC reset line is (1FFF5 7FFF5) asserted (default). Mode Register (R/W) Reading this register returns system configuration information (1FFF7 7FFF7) Bit no.
  • Page 121 You can mask each PC interrupt event separately by writing a " 1" Interrupt Mask to the corresponding bit as shown below. Register (R/W) (1FFF9 / 7FFF9) Bit no. Maskable Event (cmp. to Amiga interrupt status reg.) /MINT /GINT /CRT1INT /CRT2INT ENKBKB /LPT1INT...

  • Page 124: Bios Entry Points

    Section 4.2 BIOS Entry Points SET VIDEO MODE (AH = 00H) VIDEO ENTRY POINT VIAS/W.NT10H INPUT: AL = VIDEO MODE (0-7) 0: 40 x 25 alpha b/w 1: 40 x 25 alpha 16 colors 2: 80 x 25 alpha b/w 3: 80 x 25 alpha 16 colors 4: 320 x 200 graphics 4 colors 5: 320 x 200 graphics b/w...
  • Page 125 READ LIGHT PEN (AH = 04H) INPUT: None OUTPUT: AH = 0 if light pen not triggered. 1 if it is = Character row of light pen = Character column of light pen = Pixel row = Pixel column, best estimate SELECT ACTIVE DISPLAY PAGE (AH = 05H) INPUT: AL - NEW ACTIVE DISPLAY PAGE...
  • Page 126 OUTPUT: AL = CHAR READ (if recognized, else 0) AH = ATTRIBUTE (COLOR) (If recognized, else 0) All characters above 80h are recognized if the RAM font vector is other than 0, else not WRITE CHAR & ATTRIBUTE AT CURSOR POSITION (AH = 09H) INPUT: BH = ACTIVE DISPLAY PAGE CX = NUMBER OF TIMES TO WRITE...
  • Page 127 WRITE TELETYPE (AH = 0EH) INPUT AL = CHARACTER TO BE WRITTEN BL = FOREGROUND COLOR OF CHAR (USED ONLY IN GRAPHICS MODE) BH = REQUESTED DISPLAY PAGE (REALLY IS IGNORED) OUTPUT: None READ CURRENT VIDEO STATE (AH = 0FH) INPUT: DS = ROM data segment OUTPUT: AH = NUMBER OF SCREEN COLUMNS...
  • Page 128 RESET DISK SUBSYSTEM (AH = 00H) DISKDSR ENTRY POINT VIA S/W INT 13H OUTPUT: AH = DISK STATUS READ DISK STATUS (AH = O1H) OUTPUT: AH & AL = DISK STATUS READ SECTOR(S) (AH = 02H) WRITE SECTOR(S) (AH = 03H) VERIFY SECTOR(S) (AH = 04H) INPUT: DL = DRIVE NUMBER (0-3)
  • Page 129 INITIALIZE COMM PORT (AH=00H) EIA DSR ENTRY POINT VIAS/WINT14H INPUT: DX = Modem Control Register port AL = Baud Rate and UART control parameters BH = 0, upper bits of baud rate index OUTPUT: AH - Line Status AL = Modem Status Serial Port Control bits in AL Register Bits of AL on Entry: >...
  • Page 130 RETURN SERIAL PORT STATUS (AH = 03H) INPUT: DX = Modem Control Register port OUTPUT: AH = Line Status AL = Modem Status Serial Port Status bits returned in AX Register: AH Register: > Data Ready > Overrun Error > Parity Error >...
  • Page 131 READ SHIFT STATUS (AH – 02H) INPUT: DS = ROM data segment (0040h) OUTPUT: AL = SHIFT STATUS BYTE CASSETTE INT 15H DSR OUTPUT: AH - 86h, Error code. Carry set Interrupts off KYBDSR ENTRY POINT READ KEYBOARD INPUT (AH = 00H) VIAS/WINT16H INPUT: DS = ROM data segment (0040h)
  • Page 132 INITIALIZE PRINTER (AH = 01H) INPUT: DX = Printer Status Port address = (Printer Table contents + 1) OUTPUT: AH = Printer Status RETURN PRINTER STATUS (AH = 02H) INPUT: DX = Index to Printer table port +1 (the Status port) CH must have correct value of timeout flag OUTPUT: AH = Printer Status: >...
  • Page 133 TIMER DEVICE SERVICE ROUTINE — INT 1Ah READ CLOCK (AH = 00h) INPUT: DS = ROM data segment (0040h) OUTPUT: AL = 24-Hour Rollover flag CX = High word of Clock Count DX = Low word of Clock Count SET CLOCK (AH=01 h) INPUT: DS = ROM data segment (0040h) CX = High word of Clock Count...
  • Page 134 Section 4.3 Janus.Library This is a brief description of the janus code. This code supports low PREFACE level access to the 'janus" system — the link between a PC and an Amiga. THE PUBLIC ROUTINES ● AllocJanusMem ● CheckJanuslnt ● CleanupJanusSig Contents ●...
  • Page 135 Each jintnum may be individually enabled or disabled (this is in addi- tion to the control of setting the interrupt handler to NULL). If the interrupt is disabled then requests that are received will not generate interrupts. These requests may be detected via SetJanusRequest.
  • Page 136 ACCESS, MEM_GRAPHICACCESS, or MEM_IOACCESS. See the hardware description for the meaning of these access methods if you do not already know. FreeJanusMem( ptr, size ) A1 DO The specified memory is returned to the free pool. Some modest er- ror checking is done, and the system will Alert if there is a problem. ptr = JanusMemBase( type ) The base of the memory referred to by the type specifier is returned.
  • Page 137 This routine does the "standard" things that most users of the janus system would want It is conceivable that most people who use the janus board will use only this routine and CleanupJanusSig( ). The main purpose is to set up an interrupt handler for your inter- rupt, and translate this into an exec signal that will be sent to your task.
  • Page 138 SetupJanusSig() call. LISTINGS i86block.i — interface definitions between amiga and commodore-pc Copyright © 1986, Commodore-Amiga Inc.. All rights reserved IFND JANUS_I86BL0CK_I JANUSJ86BLOCKJ SET 1 ;All registers in this section are arranged to be read and written ;from the WordAccessOffset area of the shared memory.If you really...
  • Page 139 ; Syscall86—how the 8086/8088 wants its parameter block arranged: STRUCTURE Syscall86,0 UWORD s86_AX UWORD s86_BX UWORD s86_CX UWORD s86_DX UWORD s86_SI UWORD s86_DS UWORD s86_DI UWORD s86_ES UWORD s86_BP UWORD S86-PSW UWORD s86_INT ; 8086 int # that will be called ;...
  • Page 140 LABEL Syscall6&SIZE0F S68C0M-DOCALL EQUO ; normal case _ jsr to speci- fied Program cntr S68C0M_REMPR0C EQU1 ; kill process S68C0M_CRPR0C EQU2 ; create the process, but do not call anything ; Disk request structure for raw amiga access to 8086's disk ;...
  • Page 141 UWORD adr_BufferAddr ; offset into MEMF- _BUFFER memory for buffer UWORD adr_Err ;return code, 0 if all OK LABEL AmigaDskReq_SIZEOF ; Function codes for AmigaDskReq adr_Fnctn word: ADR_FNCTN_INIT 0 ; given nothings, sets adr_ Part to # partitions ADR_FNCTN_READ 1 ; given partition, offset. count, buffer ADFLFNCTN_WRITE 2 ;...
  • Page 142 — software conventions for janus.i Copyright © 1986, Commodore-Amiga Inc., All rights reserved IFND EXEC.TYPES_I INCLUDE "exec/types.i" ENDC EXECTYPES_I IFND EXEC-LIBRAR1ESJ INCLUDE "exec/libraries.i" ENDC EXEC_LIBRARIES_I IFND EXEC_INTERRUPTS_I INCLUDE "exec/interrupts.i" ENDC EXEC_INTERRUPTS_I JanusResource an entity which keeps track of the reset state of —...
  • Page 143 UNLOCK MACRO ; (1 — effective address of lock byte) move.b #0,1 ENDM JANUSNAME MACRO dc.b 'janus.library'.O ENDM janusreg.i —janus hardware registers (from amiga point of view) Copyright © 1986, Commodore-Amiga Inc., All rights reserved.
  • Page 144 ; Hardware interrupt bits (all bits are active low) BITDEF JINT.M1NT.0 ; mono video ram written to BITDEF JINT.GINT.1 ; color video ram written to BITDEF J1NT,CRT11NT,2 ; mono video control registers changed BITDEF J1NT.CRT21NT.3 ; color video control registers changed BITDEF JINT.ENBKB.4 ;...
  • Page 145 jio_Com2IntEnableR EQU $00dd jio_Com2DivisorLSB EQU $007f jio_Com2DivisorMSB EQU $009f jio_Com2lntlD EQU $00ff jio_Com2LineCntrl EQU $011f jio_Com2ModemCntrl EQU $013f jio_Com2LineStatus EQU $015f jio_Com2ModemStatusEQU $017f jio_Lpt1 Data EQU $019f ; data byte jio_Lptl Status EQU $01bf ; see equates below jio-Lptl Control EQU $01df ;...
  • Page 146 ; mask bits for bank region janusvar.i—the software data structure for the janus board Copyright © 1986, Commodore-Amiga Inc., All rights reserved ; All bytes described here are described in the byte order of the ; 8088. Note that words and longwords in these structures will be ;...
  • Page 147 STRUCTURE JanusMemHead.O UBYTE jmh_Lock ; lock byte between processors UBYTE jmh_padO APTR jmh_68000Base ; rptr's are relative to this UWORD jmh_8088Segment ; segment base for 8088 RPTR jmh_First ; offset to first free chunk RPTR jmh_Max ; max allowable index UWORD jmh_Free ;...
  • Page 148 Copyright © 1986, Commodore-Amiga Inc., All rights reserved 1FND JANUS_MEMRW_I JANUS.MEMRWJ SET1 ; this is the parameter block for the JSERV_READPC and JSERV_ ; READAMIGA; services — read and/or write the other processors ;...
  • Page 149 Copyright © 1986, Commodore-Amiga Inc., All rights reserved ; this is the table of hard coded services. Other services may exist ; that are dynamically allocated via AllocJanusService. ; Service numbers constrained by hardware:...
  • Page 150 APTR ss_TaskPtr ULONG ss_SigMask APTR ss_ParamPtr ULONG ss_ParamSize UWORD ss_JanuslntNum LABEL SetupSig_SIZEOF ENDC janus.h—software conventions for janus subsystem Copyright © 1986, Commodore-Amiga Inc., All rights reserved #ifndef EXEC_TYPES_I #include "exec/types.h" #endif EXEC_TYPES_I #ifndef EXEC_LIBRARIES_I #include "exec/libraries.h" #endif EXEC_LIBRARIES_I #ifndef EXEC_INTERRUPTS_I #include "exec/interrupts.h"...
  • Page 151 #define JANUSNAME "janus.library" janusreg.h—janus hardware registers (from amiga point of view) Copyright © 1986, Commodore Amiga Inc., All rights reserved /* hardware interrupt bits all bits are active low */ #define JINTB_MINT /* mono video ram written to */ #defme JINTB_GlNT...
  • Page 152 #define JINTB_LPT1INT /* parallel control register */ #define JINTB_COM2INT (6) /* serial control register */ #define JINTB_SYSINT /* software int request */ #define JINTF_MlNT (1<<0) #define JINTF_GINT (1<<1) #define JINTF_CRT1INT (1<<2) #define JINTF_CRT2INT (1<<3) #define JINTF_ENBKB (1<<4) #define JINTF_LPT1INT (1<<5) #define JlNTF_C0M2lNT (1<<6) #define JINTF_SYSINT...
  • Page 153 #definejio_RamBaseAddr 0x1fff /* r/w, sets extra ram base address */ /* now the magic bits in each register (and boy, are there a lot of them!) */ /* bits for PcIntReq, PcIntGen registers */ #define JPCINTB_IRQ1 /* active high */ #define JPCINTB_IRQ3 /* active low */ #define JPCINTB_IRQ4...
  • Page 154 Copyright © 1986, Commodore Amiga Inc., AH rights reserved /* all bytes described here are described in the byte order of the * 8088. Note that words and longwords in these structures will be * accessed from the word access space to preserve the byte order in *a word —...
  • Page 155 */#define JSETINT 0x7f memrw.i—parameter area definition for access to other processors mem Copyright © 1986, Commodore-Amiga Inc.. All rights reserved #ifndef JANUS_MEMRW_H #define JANUS_MEMRW_H ** this is the parameter block for the JSERV_READPC and JSERV_ ** READAMIGA services — read and/or write the other processors...
  • Page 156 $0002/* command that the server doesn't understand */ services.h—define common service numbers between ibm-pc and amiga Copyright © 1986. Commodore-Amiga Inc., All rights reserved #ifndef JANUS_SERV1CES_H #define JANUS_SERVICES_H /**/ /* this is the table of hard coded services. Other services may exist /* that are dynamically allocated.
  • Page 157 #define JSERV_NEWPCSERV 15 /* Amiga initiating PC side of a new service */ #endif !JANUS_SERVICES_H #ifndef JANUS_SETUPSIG_H#define setupsig.i—data structure for SetupJanusSig( ) routine Copyright © 1986, Commodore-Amiga Inc., All rights reserved #ifndef EXEC_TYPES_H #include "exec/types.h" #endif #ifndef EXEC_INTERRUPTS_H #include "exec/interrupts.h"...
  • Page 158 This service is called via INT JANUS. PC JANUS SERVICE AH contains a function code J_GET_SERVICE Gets a new Service Number Expects: nothing Returns: AL : New Service Number to use - 1 if no service available (J_NO_SERVICE) J_GET_BASE Gets Segments & offset of Janus Memory Expects: AL : Janus Service Number Returns:...
  • Page 159 J_SET_SERVICE Set an address for a far call for that service Expects: AL : Janus Service Number to support ES:DX: Entry address for FAR call Returns: Status (J_OK, J_N(XSERV1CE) J_STOP_SERVICE Prevents AMIGA from using the far call (see above) for this function and releases this Service Number.
  • Page 160 J_FREE_MEM equ 3 J_SET_PARAM equ 4 J_SET_SERV1CE equ 5 J_STOP_SERVICE equ 6 J_CALL_AMIGA equ 7 J_WAIT_AM1GA equ 8 J_CHECK_AMIGA equ 9 Status Returns: J_NO_SERVICE equ 0ffh ; no service available J_PENDING equ 0 ; after J_CALL_AMIGA and J_CHECK_AMIGA J.FINISHED equ 1 ;...
  • Page 161 ADR ERR SEEK seek error ADR_ERR_READ read went wrong ADR_ERR_WRITE 10 write error ADR_ERR_LOCKED EQU 11 file is locked...

  • Page 162: Section 5 Amiga Hard Disk/Scsi Controller

    Section 5 Amiga Hard Disk/SCSI Controller The Amiga Hard Disk/SCSI Controller is an intelligent high perfor- DESCRIPTION mance controller designed to interface both ST506 hard disk drives and SCSI devices to the Amiga expansion bus architecture. A back- ground command processor provides high level command interpre- tation minimizing Host intervention.
  • Page 163 SCSI ANSI X3T9.2 compatible Macintosh Plus compatible connector Host Interface Amiga expansion bus compatible Full auto-config compatibility Power Requirements + 5 Volts ± 5%, 3 Amps. Max. Environmental Ambient Temperature: 0 - 55 Deg. C. Relative Humidity: 20% - 80% The following tables list the pin assignments for the controller CONNECTOR PIN board.
  • Page 164 Table 5-2 Connector JO Disk Control Signal Pin Assignments Ground Signal Return Signal Name Head Select 3 Head Select 2 Write Gate Seek Complete Track 00 Write Fault Head Select 2 Reserved Head Select 1 Index Ready Step Drive Select 1 Drive Select 2 Reserved Reserved...
  • Page 165 Information on initializing the DMA appears later in this section. The DMA is a Commodore custom LSI chip (8727) with byte to word funneling and a built in 64 byte FIFO. The internal 64 byte FIFO permits real time data transfer to and from the host without holding the bus for an entire sector transfer.

  • Page 166: Section 6 Custom Chips

    The design that has gone into this aspect of the controller has been to enhance performance and increase flexibility while reducing cost As a result, the majority of operations have been placed in firmware. The only functions performed by "hardware" are those that are too fast for the processor.
  • Page 167 TWO INDEX TIMEOUT This function insures accurate control over the number of attempts to find a header (i.e., it is not "mislead" by counting false address marks). MFM ENCODE The DJC converts all parallel data to serial and then to MFM. This function is followed by Precomp, if selected.
  • Page 168 Figure 5.1 describes the format of a typical sector. Sector Format Figure 5.1 Typical Sector Format SYNC1 A1 FD HEADER WRITE SPLICE SYNC 2 A1 F8 DATA 4 BYTE ECC 512 BYTES ADDRESS MARK 4 BYTE HEADER BYTE 1 = HEAD # BYTE 2 = TRACK ADDRESS BYTE 3 = SECTOR # BYTE 4 = CRC...
  • Page 169 In data recovery and error correction the ECC syndrome must be stable in order to perform a correction. This insures that multiple attempts are made to recover marginal data before correction data is applied and further reduces the probability of miscorrection on long (greater than 12-bit) error bursts.
  • Page 170 WRITE READ 40/42 15/14/13/12 15/14/13/12 Interrupt enable Interrupt enable DON’T CARE *SSEL MUST BE ZERO MRESET *CCBP bit *HCBP bit INT2 PENDING not defined ZERO not defined ZERO not defined INT FOLLOW not defined *Signals unique to Amiga Hard Disk/SCSI Controller. SSEL Used to select SCSI controller or to ST605 controller.

  • Page 171: Host Interface

    HOST INTERFACE PROTOCOL Interface Protocol The host interface is via a DMA controller. This DMA device is con- trolled by the Z80A on the disk controller board or 68000 (host). On the host side there are counters for the address bus that are preset before the beginning of each transfer.
  • Page 172 Table 5-4. DMA States Data Strobed Brief Functional DESCRIPTION Data Valid by PCSS- PCSD-(R/F) FB 1111 1011 Load upper DMA address latch FD 1111 1101Load mid DMA address latch FE 1111 1110 Load low DMA address latch; start DMA on rising edge of LDO; block mode XFER F7 1111 1111 Open path to int.
  • Page 173 This state opens a path to an internal FIFO that is 64 bytes in FIFO Access (F7) length. The failing edge of PCSD- will start to shift data out of the FIFO for a read or shift data into the FIFO on the rising edge of PCSD- if the R/W- was set low with LD2.
  • Page 174 This will cause the assertion of the host vectored interrupt line to its Command Complete active low state to indicate the completion of a command by the Acknowledge (BF) HDC. This will set the internal DMA circuit into a single word tranfer. On Word Transfer (DF) completion of the word transfer, the DMA resets to a block transfer mode.
  • Page 175 contains EO or AO, before attempting to clear the FIFO and retrans- mit the block of data, if necesssary. If the FIFO cannot be cleared after within 20 mS, the command will be terminated in the normal manner, if possible. Step 3: Reading The If byte 12 is an FF, the rest of the command block is retrieved by the CMD.
  • Page 176 Table 5.5. Host Command Block BYTE WORD Command Class OP Code Logical Unit Number Logical Sector Address (High) Logical Sector Address (Middle) Logical Sector Address (Low) Block (sector) Count Control Byte (reserved in DMA spec) High Order DMA DB Address (A23-A17) Mid Order DMA DB Address (A15-A9) Low Order DMA DB Address (A1-A8) Reserved...
  • Page 177 A logical sector address is a 21 bit unsigned integer that specifies a Logical Sector Address unique physical sector. The one-to-one correspondence between the set of logical sector addresses and the set of physical sectors is com- puted by the HDC from the Cylinder (C), Head (H), and Sector (S) address, as well as the drive parameters, heads per drive (HD) and Sectors per track (ST): L = ((( C * HD ) * H ) * ST ) + S...
  • Page 178 At the completion of each command the HDC will return status in Status and Error Bytes the last four bytes (12-15) of the command block. The status format is similar to that returned by the 'Request Sense' SCSI command. This four byte block contains error and status information pertaining to the last block of data transferred or a non-disk operation executed by the HDC.
  • Page 179 No Error Error Code Description A code of 00 or 80 is returned if no errors were detected during the execution of the last operation. No Index (1) The HDC does not detect index signal from drive. Seek in Progress (2) This error code is only returned by the test drive ready command when the target drive is a hard disk that supports buffered seeks.
  • Page 180 sists after 8 attempts, an auto-restore is performed, followed by a reseek, and another 8 attempts to read the desired LSA. Sector Not Found, Read (13) The HDC found the correct cylinder and head but not the target sec- tor. Sector Not Found, Write (14) The HDC found the correct cylinder and head but not the target sec- tor.
  • Page 181 All commands executed by the HDC are summarized in the table be- COMMAND low. Fields of the command block not specified are don't cares. Fol- DESCRIPTION lowing this summary is a generalized description of the commands. Table 5-6. Command Summary Command Class LADD...
  • Page 182 The Restore command positions the heads to cylinder 0. It is usually issued by the host when the drive has been turned on, or before a format drive operation is initiated by the host. Possible Error Codes No error, invalid command. Track 0 not found, drive not ready, write fault, DMA error.
  • Page 183 No error, invalid command, invalid sector address, drive not ready, seek not complete, write fault, invalid LUN, DMA error. During this command the sector is set up by the host to contain addi Interleave tional parameter information instead of data. Each sector requires a Considerations two byte sequence.
  • Page 184 These numbers can be from 00 to 10 (hex), or 17 sectors per track or any number that the host wishes to specify that meets the drive track capacity. Bad block marks are shown for sector numbers 1 and 4 in all four interleave factors illustrated. The other requirement of the host is to provide the logical sector number.
  • Page 185 To maximize data read back efficiency and maintain the interleave factor of one, as closely as possible, it is required that the physical sector numbers be offset by a sector from track to track, (see table) so that the HDC has a sector length available for overhead to switch heads while on the same cylinder.
  • Page 186 No error, invalid command, invalid sector address, invalid LUN, drive not ready, write fault, DMA error. Set Drive Parameters Action (Class 0, Opcode C) This command points to a 6 byte block of memory, specified by bytes 6 and 7 of the command block, that sets the following parameters for both of the hard disk drives (logical units 0 and 1): Table 5-9.
  • Page 187 This four bit field can be used to specify options as indicated below: Bit 7 5 bit correction span (default value) 11 bit correction span Bit 6 Retries & ECC enabled (default value) Retries & ECC disabled Bit 5 Not Used Bit 4 Not Used Step Rate...
  • Page 188 Since the host R/W bit. and address bits A23-A17, form the data byte for the host LD2- counter, the DMA high and middle order ad- dress bytes are shifted right 1 bit position before being used. Since a copy of the previous address is not maintained, the command status is returned to the new address location specified and not the old one.
  • Page 189 Possible Error Codes No error, invalid commands, invalid sector address, invalid LUN, IDNF error, bad block mark, write fault, seek not complete, drive not ready, DMA error.

  • Page 190: Fat Agnus Chip

    Section 6 Fat Agnus Chip This specification describes the Fat Agnus chip, an N-channel HMOS DESCRIPTION DMA Controller. This IC device is able to produce, in a 68000 micro- processor environment, DMA addresses by using a RAM Address Generator and a Register Address Encoder. This device contains 25 DMA channel controllers, including the Blitter, Bitplanes, Copper, Audio, Sprites.
  • Page 191 This IC device is configured in a standard 84 pin plastic chip carrier CONFIGURATION package. Custom Animation Chip Fat Agnus RST∗ INT3 DMAL BLS∗ DBR∗ RGEN∗ AS∗ RAMEN∗ RGA8 RGA7 RGA6 RAS0∗ RGA5 RAS1∗ RGA4 CASU∗ RGA3 CASL∗ RGA2 Figure 6.1 Configuration...
  • Page 192 Clock Generation ADDRESS (A1-A19) UDS/LDS RAM Control RAS0/1 DSR∗ MA0-MA8 Logic ∗ RAMEN CASL/U ∗ Priority A1-A18 Buffer Control Logic Coprocessor (Copper) (16) Figure 6.2 Block Diagram...
  • Page 193 Table 6-1 Pin Description SIGNAL NAME NUMBER DIRECTION DESCRIPTION A19-A1 59 thru 77 Address bus—A1 to A8 are used by the processor to select the internal registers and put an address code on the RGA lines to select registers outside the device.
  • Page 194 SIGNAL NAME NUMBER DIRECTION DESCRIPTION MA0-MA8 43 thru 51 Output bus. This 9 bit output bus provides multi- plexed addresses to DRAMs. This bus operates in two cycles. The first cycle provides the DRAMs with the row address, the second cycle with the column ad- dress.
  • Page 195 SIGNAL NAME NUMBER DIRECTION DESCRIPTION RGA8-RGA1 26 thru 33 Output bus. The 8 bit output bus allows the device and the processor to access registers located outside the device. HSY* This line is bidirectional and buffered. This signal is the horizontal synchronization pulse and is NTSC compatible.
  • Page 196 SIGNAL NAME NUMBER DIRECTION DESCRIPTION XCLKEN* This input is used to select the master clock to the device. If it is high, the 28MHz input is enabled; if low, the XCLK is enabled. This signal is a clock, which is obtained after dividing the 28.63 MHZ clock by eight It is also known as the color clock frequency for NTSC applications.
  • Page 197 The priority control logic looks at the pipe-lined DMA requests from each controller and stages the DMA cycles based upon their pro- grammed priority and sync counter time slot Then it signals the pro- cessor to get off the bus by asserting the DBR line. The following is a brief description of the device's major operational modes.
  • Page 198 Some computer bitmap displays are organized so that the bitplanes Bitplane Addressing for each pixel are all located within the same address. This is called pixel addressing. If the entire data word of one address is used for a single pixel with 8 bit planes, the data word will look like this, (num- bers are bitplanes): 12345678--------- The data compression can be improved by packing more than one...
  • Page 199 Figure 6.4 shows a typical DMA channel; almost all channels have RAM as source and chip registers as destination. 8370/ EX TER N A L R A M R EG I STER 16 BI T D ATA BU S D EST SO U R C E R G A A D D R ESS...
  • Page 200 The bitplane controller continuously B-BITPLANE (SIX (6) (during display) transfers display data CHANNELS) from memory to display buffer registers. There are six DMA channels to handle the data from six independent bit planes. The buffers convert this bitplane data into pixel data for the display.
  • Page 201 There are eight independent Sprite E-SPRITES (EIGHT (8) controllers, each with its own DMA CHANNELS) channel and its own dedicated time slot for DMA data transfer. Sprites are line buffered objects that can move very fast because of their position are controlled by hardware registers and compactors.
  • Page 202 The device generates RAM addresses from two sources, the proces- RAM and Register sor or from the device performing DMA cycles selected by a multi- Addressing plexer. This multiplexer allows the processor to access RAM when AS* and RAMEN* are both low. At this time, the device also multi- plexes the processor address (Al -Al 8) onto the MA bus.
  • Page 203 This pair of registers contains the 18 bit starting address (location) of Audio channel x (x = 0,1,2.3) DMA data. This is not a pointer register and therefore only needs to be reloaded if a different memory location is to be outputted. Blitter pointer to x (high 3 bits) BLT x PTH Blitter pointer to x (low 15 bits)
  • Page 204 LINE DRAW: BLTADAT is used as an index register and must be pre loaded with 8000. BLTBDAT is used for texture. It must be preloaded with FF if no texture (solid line) is desired. Blitter destination data register BLTDDAT This register holds the data resulting from each word of Blitter operation until it is sent to a RAM destination.
  • Page 205 LINE DRAW: LINE MODE (line draw) BIT # BLTCON0 BLTCON1 START3 START2 START1 START0 SIGN SING LINE(=1) START3-0 Starting point of line (0 thru 15 hex) LF7-0 Logic function minterm select lines should be preloaded with 4A in order to select the equation D = (AC + ABC).
  • Page 206 This register contains the width and height of the blitter operation (in line mode width must = 2, height = line length). Writing to this register starts the Blitter, and should be done last after all pointers and control registers have been initialized. BIT# 15,14, 13, 12, 11, IO, 09,08, 07,06.05, 04.
  • Page 207 BIT# BPLCON0 HIRES BPU2 BPU1 BPU0 HOMOD DBPLF COLOR GAUD LPEN LACE ERSY HIRES = High resolution (640) mode = Bit plane use code 000-110 (NONE through 6 inclusive) HOMOD = Hold and Modify mode DBLPF = Double playfield (PF1 =odd. PF2 = even bit planes) COLOR = Composite video COLOR enable...
  • Page 208 COP1LCH Copper first location register (high 3 bits) COP1LCL Copper first location register (low 15 bits) COP2LCH Copper second location register (high 3 bits) COP2LCL Copper second location register (low 15 bits) Copper instruction fetch identify COP1NS This is a dummy address that is generated by the Copper whenever it is loading instructions into its own instruction register.
  • Page 209 *NOTE BFD = Blitter finished disable. When this bit is true, the Blitter Finished flag will have no effect on the Copper. When this bit is zero, the Blitter Finished flag must be true (in addition to the rest of the bit comparisons) before the Copper can exit from its wait state, or skip over an instruction.
  • Page 210 These registers control the horizontal tinning of the beginning and end of the Bit Plane DMA display data fetch. The vertical Bit Plane DMA timing is identical to the Display windows described above. The Bit Plane Modulos are dependent on the Bit Plane horizontal size, and on this data fetch window size.
  • Page 211 BIT# FUNCTION DESCRIPTION DMAEN Enable all DMA below. DPLEN Bit Plane DMA enable. COPEN Copper DMA enable. BLTEN Blitter DMA enable. SPREN Sprite DMA enable. DSKEN Disk DMA enable. AUD3EN Audio channel 3 DMA enable. AUD2EN Audio channel 2 DMA enable. AUD1EN Audio channel 1 DMA enable.
  • Page 212 BIT# FUNCTION 15-08 EV7-EV0 End (stop) vert.value.low 8 bits Sprite attach control bit (odd sprites) 06-04 Not used Start vert, value high bit End (stop) vert, value high bit Start horiz. value low bit VPOSR Read vertical most significant bit (and frame flop) Write vertical most significant bit (and frame VPOSW...
  • Page 213 DMA Time Slot Allocation/Horizontal Line NOTES 1) These operations only take slots if the associated operation is be ing performed Note: Copper Data Move instructions require 4 slots. Copper Wait instructions require 6 slots. 2) This cycle 0 appears to exclude one of the memory refresh cycles. This is not the case.
  • Page 214 DMA Time Slot Hardware stop installed here. Data fetch cannot begin any Allocation/Horizontal sooner than cycle 18. This allows the user to wipe out most of Line (Cont`d) the sprites if desired (by defining an extra-wide display) but leaves the audio and disk DMA untouched. ( c o n t i n u e s b e l o w ) These operations only take slots if the...
  • Page 215 DMA Time Slot Data fetch start can only be specified at even multiples of 8 Allocation/Horizontal clocks. This is the clock position which should be specified for Line (Cont`d) the normal width display. (20 word fetch for 320 pixel, 40 word fetch for 640 pixel width).
  • Page 216 The 8520 Chip 8520 FLAG Figure 6.5. 8520 Pin Configuration...
  • Page 217 D -D DATA BUS BUFFERS PA -PA BUFFERS SERIAL BUFFER PORT DORA BUFFERS BUFFER B -P BUFFERS TOD/ ALARM BUFFER DORB TIMER B FLAC FLAG BUFFER TIMER A INT/ BUFFER MASK CHIP ACESS CONTROL 02 CS Figure 6.6. 8520 Block Diagram...
  • Page 218 W R I TE TI M I N G D I A G R A M TCYC TCHW TCLW 02 INPUT PERIPHERAL DATA OUT TWCS TADH TADS RS3-RS0 TRWS TRWH DATA IN D87-D80 R EA D TI M I N G D I A G R A M 02 INPUT PORT IN TWCS...
  • Page 219 INTERFACE SIGNALS The 02 clock is a TTL compatible input used for internal device oper- 02-Clock Input ation and as a timing reference for communicating with the system data bus. CS-Chip Select Input The CS input controls the activity of the 8520. A low level on CS while 02 is high causes the device to respond to signals on the R/W and address (RS) lines.

  • Page 220: Functional Description

    REGISTER MAP Peripheral Data Reg. A Peripheral Data Reg. B DDRA Data Direction Reg. A DDRB Data Direction Reg. B TA LO Timer A Low Register TA HI Timer A High Register TB LO Timer B Low Register TB HI Timer B High Register Event LSB Event 8-15...
  • Page 221 Reg Name DDRA DPA7 DPA6 DPA5 DPA4 DPA3 DPA2 DPA1 DPAO DDRB DPB7 DPB6 DPB5 DPB4 DPB3 DPB2 DPB1 DPBO Each interval timer consists of a 16-bit read-only Timer Counter and Interval Timers (Timer a 16-bit write-only Timer Latch. Data written to the timer are A, Timer B) latched in the Timer Latch, while data read from the timer are the present contents of the Timer Counter.
  • Page 222 A strobe bit allows the timer latch to be loaded into the timer Force Load counter at any time, whether the timer is running or not Input Mode Control bits allow selection of the clock used to decrement the timer. TIMER A can count 02 pulses or external pulses applied to the CNT pin.
  • Page 223 read sequence. All TOD registers latch on a read of MSB event and remain latched until after a read of LSB Event The TOD clock contin- ues to count when the output registers are latched. If only one regis- ter is to be read, there is no carry problem and the register can be read "on the fly", provided that any read of MSB Event is followed by a read of LSB Event to disable the latching.
  • Page 224 drain, with passive pullups, to allow such a common bus. Protocol for slave/master selection can be transmitted over the serial bus. or via dedicated handshaking lines. NAME There are five sources of interrupts on the 8520: underflow from Interrupt Control (ICR) TIMER A.
  • Page 225 Control Registers There are two control registers in the 8520: CRA and CRB. CRA is associated with TIMER A and CRB is associated with TIMER B. The register format is as follows: CRA: NAME FUNCTION START 1 = START TIMER A. 0 = STOP TIMER A. This bit is automatically reset when underflow occurs during one-shot mode.
  • Page 226 Section 7.1 Clock/Calendar Information The clock/calendar is based on the OKI MSM6242RS Direct Bus Connected-Type Real Time Clock Chip. The A2000 features a real time clock with a perpetual calendar which is capable of reading and writing "YEAR", "MONTH", "DAY", "WEEK", "HOUR", "MINUTE"...
  • Page 227 REGISTER TABLE Data Count value Description 0 ~ 9 1-second digit register 0 ~ 5 10-second digit register 0 ~ 9 1-minute digit register 0 ~ 5 10-minute digit register 0 ~ 9 1-hour digit register 0 ~ 2 PM/AM, 10-hour digit or O register to 1...

  • Page 228: Power Budgets

    Section 7.2 Power Budgets A2000/B2000 POWER SUPPLY: B2000 POWER BUDGET All of the specifications herein are suggested. When it comes right down to it, the machine is being powered by a well-defined supply. the specifications of which will follow. If you're careful not to exceed the suggested load for any port, you'll be able to fully load every port.
  • Page 229 EXTERNAL PORTS: Video Port 10mA 100mA 100mA Floppy Port [1] 250mA 350mA Parallel Port [3] 10mA Serial Port 25mA 25mA Keyboard Port [4] 250mA Mouse Port 50mA INTERNAL SLOTS: CoProcessor Slot [6] 2.0A 40mA 40mA 35mA Expansion Slot [6] 2.0A 40mA 40mA 35mA...
  • Page 230 PARALLEL PORT: A500 Power Budget 10mA from pin 14 ( + 5V) (47Ω series resistor to prevent damage if printer grounds this line) SERIAL PORT: 20mA from pin 9 (+ 12V) 20mA from pin 10 (-12V) (47Ω series resistor to limit current) VIDEO PORT: 100mA from pin 23 ( + 5V) 100mA from pin 22 ( + 12V)

  • Page 232: A2000 Pal Equations

    REV.2 FRANK ULLMANN 03-09-86 MEM- AND DTACK-DECODER FOR A2500 MAINBOARD (U26) ASSY 380... COMMODORE BSW ! ! PRELIMENARY ! ! A23 A22 A21 A20 A19 A18 PRW AS DBR OVL OVR GND C1 C3 VPA MYRAME CLKE RGAE RE DTACK BLS ROME XRDY VCC IF (OVR) /VPA = /AS*A23*/A22*A21 ;...
  • Page 233 /ROME = /AS*A23*A22*A21*A20*A19*OVR*PRW ; $FB0000-FFFFFF + /AS*A23*A22*A21*/A20*/A19*OVR*PRW ; $E00000-E7FFFF + /AS*/A23*/A22*/A21*/A20*/A19*OVR*OVL*PRW ; $000000-07FFFF + /AS*/A23*/A22*/A21*A20*A19*OVL*OVR*PRW ; $180000-1FFFFF /CLKE = /AS*A23*A22*/A21*A20*A19*/A18*OVR ; $D80000-DBFFFF DESCRIPTION THE CLOCK IS NOW TILED THROUGHOUT THE SPACE $D80000-DBFFFF. IF MORE PRECISE SELECTION TO $D80000 $D8FFFF IS REALLY WEEDED, THEN THIS MUST BE DONE EXTERNALLY USING THE /CS INPUT ON THE CLOCK CHIP.
  • Page 234 PART NO.: 380 XXX-01 DESCRPT.:PALCAS REV.1 FRANK ULLMANN 08-29-86 RAM/ROM-DECODER FOR A2500 MAINBOARD REV.2 (U27) ASSY 380... COMMODORE BSW !! PRELIMENARY !! ARW C1 C3 PRW UDS LDS RE RGAE CLKE GND DBR CLKR RRW LCEN UCEN CDR CDW DAE CLKW VCC...
  • Page 235 PART NO.: 380715-2 DESCRPT.: PAL BUFFER CONTROL REV.2 HEINZ ULLRICH 06-18-87 PAL BUFFER CONTROL FOR A2500 (U5) FOR PRODUCTION-PCB COMMODORE BSW SLV1 SLV2 SLV3 SLV4 SLV5 OVR RD BAS RESET A23 A22 GND A21 A20 D2P A19 BERR OWN DS NCOLLIS PROC DBOE ASQ VCC...
  • Page 236 PART NO.: DESCRPT.:PAL ARBITRATE A2500 REV.1 FRANK ULLMANN 05-22-86 PAL ARBITRATE FOR A2500 (U ) FOR PRODUCTION-PCB COMMODORE BSW 7M BAS RES BGIN BR5 BR4 BR3 BR2 BR1 GND NC BASD BGOLD BG5 BG4 BG3 BG2 BG1 BR VCC /BG1 = RES*/BGIN*BG0LD*/BR1 ;...
  • Page 238 Section 7.4 List of B2000 Motherboard Jumpers J101 This jumper determines the high-order address bit for Fat 3 2 1 3 2 1 Agnus. In its normal position shown the high-order bit is A23; in its other position, this bit is A19. The current Fat Agnus chip requires the A23 signal for proper management of the memory at $C00000.
  • Page 239 Appendix A Diagrams This appendix contains the following figures: CONTENTS The example backplane (discussed in Section 3.1) The example PIC {discussed in Section 3.1) A500 exterior, featuring the 86-pin expansion connector Amiga 2000 expansion board layout Amiga 2000 form factor (including 100-pin connector) Amiga 2000 video card 86-Pin slot expansion board A2000/B2000 keyboard connector pinout...

This manual is also suitable for:

Amiga a2000

Table of Contents