Functional Description - Commodore Amiga A500 Technical Reference Manual

REGISTER MAP
RS3 RS2
0 0
0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
1 0
1 0
1 0
1 1
1 1
1 1
1 1
FUNCTIONAL
DESCRIPTION
I/O Ports (PRA, PRB,
DDRA, DDRB)
Handshaking
RS1 RS0 REG
0 0 0
0 1 1
1 0 2
1 1 3
0 0 4
0 1 5
1 0 6
1 1 7
0 0 8
0 1 9
1 0 A
1 1 B
0 0 C
0 1 D
1 0 E
1 1 F
Ports A and B each consist of an 8-bit Peripheral Data Register (PR)
and an 8-bit Data Direction Register (DDR). If a bit in the DDR is set
to the corresponding bit in the PR is an output if a DDR bit is set to
zero, the corresponding PR bit is defined as an input. On a READ,
the PR reflects the information present on the actual port pins
(PAO-PA7, PB0-PB7) for both input and output bits. Port A has
both passive and active pullup devices, providing both CMOS and
TTL compatibility. It can drive 2 TTL loads. Port B has only passive
pullup devices and has a much higher current-sinking capability.
Handshaking on data transfers can be accomplished using the PC
output pin and the FLAG input pin. PC will go low on the 3rd cycle
after a PORT B access. This signal can be used to indicate '"data
ready" at PORT B or "data accepted" from PORT B. Handshaking on
a 16-bit data transfers (using both PORT A and PORT B) is possible
by always reading or writing PORT A first. FLAG is a negative edge
sensitive input which can be used for receiving the PC output from
another 8520 or as a general purpose interrupt input. Any negative
transition on FLAG will set the FLAG interrupt bit.
PRA Peripheral Data Reg. A
PRB Peripheral Data Reg. B
DDRA Data Direction Reg. A
DDRB Data Direction Reg. B
TA LO Timer A Low Register
TA HI Timer A High Register
TB LO Timer B Low Register
TB HI Timer B High Register
Event LSB
Event 8-15
Event MSB
No Connect
SDR Serial Data Register
ICR Interrupt Control Register
CRA Control Register A
CRB Control Register B
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