8254 Timer Control Register - VersaLogic Iguana VL-EPIC-25 Reference Manual

8254 Timer Control Register

This register is used to set modes related to the inputs on the 8254 Timers.
TIMCNTRL (Read/Write) CA5h
D7
TIM5GATE TIM4GATE
Bit Mnemonic
D7 TIM5GATE
D6 TIM4GATE
D5 TIM3GATE
D4 TM4MODE
D3 TM4SEL
D2 TM3SEL
D1-D0 Reserved
An 8254 timer is implemented in the PLD (see Table 25: On-Board I/O Devices for I/O
addresses). It contains three independent 16-bit timers. It is fully software compatible with the
Intel 8254, except that only binary counting modes are implemented (the BCD control bit is
implemented but ignored). See the
register definitions and programming information.
There is an option to cascade two of the timers together in a 32-bit mode. The timers are
identified as Timer 3, 4, and 5. When Timers 4 and 5 are cascaded, Timer 4 is the LS 16-bits and
Timer 5 is the MS 16-bits. In this 32-bit cascade mode the timer output of Timer 4 feeds the
clock input of Timer 5. In this mode Timer 4 would normally be set so that it generates a clock
after counting the full 16-bit range, but there is no requirement to do this.
VL-EPIC-25 Reference Manual
D6 D5 D4
TIM3GATE TM4MODE
Table 31: 8254 Timer Control Register Bit Assignments
Description
Sets the level on the Gate input for the 8254 Timer #5.
0 = GCTC5 Gate is disabled (set to a logic 0)
1 = GCTC5 Gate is enabled (set to a logic 1)
Sets the level on the Gate input for the 8254 Timer #4.
0 = GCTC4 Gate is disabled (set to a logic 0)
1 = GCTC4 Gate is enabled (set to a logic 1)
Sets the level on the Gate input for the 8254 Timer #3.
0 = GCTC3 Gate is disabled (set to a logic 0)
1 = GCTC3 Gate is enabled (set to a logic 1)
Configure how the 8254 Timer #4 and #5 are used.
0 – Timer #4 is cascaded with Timer #5 for a 32-bit timer
1 – Timer #4 operates in normal 16-bit mode
Configure the clock source for 8254 Timer #4.
0 – Timer #4 input clock is 4.167 MHz internal clock (PCI clock divided by 8)
1 – Timer #4 input clock is from User I/O connector Input ICTC4
Configure the clock source for 8254 Timer #3.
0 – Timer #3 input clock is 4.167 MHz internal clock (PCI clock divided by 8)
1 – Timer #3 input clock is from User I/O connector Input ICTC3
These bits are reserved. Only write 0 to these bits and ignore all read values.
Intel 82C54 Programmable Interval Timer Datasheet
D3 D2
TM4SEL TM3SEL Reserved
Special Registers
D1 D0
Reserved
for
63