Related Manuals for VersaLogic VL-EPU-4562
Summary of Contents for VersaLogic VL-EPU-4562
- Page 1 Programmer’s Reference Manual REV. May 2018 Blackbird (VL-EPU-4562) Intel Core™-based Embedded ® Processing Unit with SATA, Dual Ethernet, USB, Digital I/O, Serial, Video, Mini PCIe Sockets, SPX, Trusted Platform Module.
- Page 2 Copyright © 2017-2018 VersaLogic Corp. All rights reserved. Notice: Although every effort has been made to ensure this document is error-free, VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose.
- Page 3 Data sheets and manufacturers’ links for chips used in this product BIOS information and upgrades Utility routines and benchmark software The VersaTech KnowledgeBase is an invaluable resource for resolving technical issues with your VersaLogic product. VersaTech KnowledgeBase EPU-4562 Programmer’s Reference Manual...
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Page 4: Table Of Contents
Contents Introduction ........................1 Related Documents ......................1 System Resources ......................2 Interrupts ..........................2 FPGA I/O Space ......................... 2 FPGA Registers ......................4 Register Access Key ......................4 Reset Status Key ......................... 4 FPGA Register Map ......................5 FPGA Register Descriptions....................8 Product Information Registers ................ - Page 5 Contents Table 10: MISCSR2 – Misc. Control Register #2 ............15 Table 11: MISCSR3 – Misc. Control Register #3 ............16 Table 11: MISCSR4 – Misc. Control Register #4 ............17 Table 12: SPI Interface Control Register ................18 Table 13: SPI Interface Status Register ................19 Table 14: SPI –...
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Page 6: Introduction
The following documents are available on the EPU-4562 Product Support Web Page: VL-EPU-4562 Hardware Reference Manual – provides information on the board’s hardware features including connectors and all interfaces. Operating System compatibility and software package downloads are available at the VersaLogic page. -
Page 7: System Resources
System Resources Interrupts The LPC SERIRQ is used for interrupt interface to the Skylake SoC. Each of the following devices can have an IRQ interrupt assigned to it and each with an interrupt enable control for IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, and IRQ11: ... -
Page 8: Table 1: Fpga I/O Map
System Resources and Maps Table 1: FPGA I/O Map Address Range Device Size 0x1C80 – 0x1CBB FPGA registers 60 bytes 0x1CBC – 0x1CBF 8254 timer address registers 4 bytes EPU-4562 Programmer’s Reference Manual... -
Page 9: Fpga Registers
FPGA Registers This chapter describes the FPGA registers. Table 2 (beginning on the following page) lists all 64 FPGA registers Table 3 (refer to page 8) through Table 48 provide bit-level information on the individual FPGA registers Register Access Key Key: Read/Write Read-Only... -
Page 10: Fpga Register Map
FPGA Register Map Table 2: FPGA Register Map Address Offset Reset Platform PLED PRODUCT_CODE REV_LEVEL EXTEMP CUSTOM BETA Platform BIOS_JMP BIOS_OR BIOS_SEL LED_DEBUG WORKVER WP_JMP WP_EN Platform IRQEN IRQSEL2 IRQSEL1 IRQSEL0 IMASK_TC5 IMASK_TC4 IMASK_TC3 Platform INTRTEST TMRTEST TMRIN4 TMRIN3 ISTAT_TC5 ISTAT_TC4 ISTAT_TC3 Platform... - Page 11 FPGA Registers Address Offset Reset Platform IMASK_DIO8 IMASK_DIO7 IMASK_DIO6 IMASK_DIO5 IMASK_DIO4 IMASK_DIO3 IMASK_DIO2 IMASK_DIO1 Platform IMASK_DIO16 IMASK_DIO15 IMASK_DIO14 IMASK_DIO13 IMASK_DIO12 IMASK_DIO11 IMASK_DIO10 IMASK_DIO9 Platform ISTAT_DIO8 ISTAT_DIO7 ISTAT_DIO6 ISTAT_DIO5 ISTAT_DIO4 ISTAT_DIO3 ISTAT_DIO2 ISTAT_DIO1 Platform ISTAT_DIO16 ISTAT_DIO15 ISTAT_DIO14 ISTAT_DIO13 ISTAT_DIO12 ISTAT_DIO11 ISTAT_DIO10 ISTAT_DIO9 Platform IRQEN...
- Page 12 FPGA Registers Address Offset Reset Platform <============> Platform <============> Platform <============> Platform <============> EPU-4562 Programmer’s Reference Manual...
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Page 13: Fpga Register Descriptions
FPGA Register Descriptions Key: Read/Write Read-Only R/WC Read-Status/Write-1-to-Clear Write-Only Read-Only and clear-to-0 after reading Not implemented. Returns 0 when read. Writes are RSVD ignored RODUCT NFORMATION EGISTERS This register drives the PLED on the paddleboard. It also provides read access to the product code. -
Page 14: Bios And Jumper Status Register
FPGA Registers BIOS UMPER TATUS EGISTER Table 5: SCR –Status/Control Register Identifier Access Default Description BIOS_JMP Status of the external BIOS switch (jumper): 1 – Primary BIOS selected (the one on the COM Module) 0 – Backup BIOS selected (the one on the base board) Note: For this implementation this reads the status of the jumper all the time is essentially the “AND”... -
Page 15: Timer Registers
FPGA Registers IMER EGISTERS The FPGA implements an 8254-compatible timer/counter that includes three 16-bit timers. Table 6: TICR – 8254 Timer Interrupt Control Register Identifier Access Default Description 8254 Timer interrupt enable/disable: IRQEN 0 – Interrupts disabled 1 – Interrupts enabled 8254 Timer interrupt IRQ select in LPC SERIRQ: 000 –... -
Page 16: Table 7: Tisr - 8254 Timer Interrupt Status Register
FPGA Registers Table 7: TISR – 8254 Timer Interrupt Status Register Identifier Access Default Description RESERVED Reserved. Writes are ignored; reads always return 0. RESERVED Reserved. Writes are ignored; reads always return 0. RESERVED Reserved. Writes are ignored; reads always return 0. RESERVED Reserved. -
Page 17: Table 8: Tcr - 8254 Timer Control Register
FPGA Registers Table 8: TCR – 8254 Timer Control Register Identifier Access Default Description Debug/Test Only: Controls the “gate” signal on 8254 timer #5 when not using an external gate signal: 0 – Gate on signal GCTC5 is disabled TMR5GATE 1 –... -
Page 18: Miscellaneous Fpga Registers
FPGA Registers FPGA R ISCELLANEOUS EGISTERS MISCSR1 – Miscellaneous Control Register #1 This is a register in the always-on power well of the FPGA. It holds its state during sleep modes and can only be reset by a power cycle. This is a placeholder register for features like pushing the power-button and also for software initiated resets should those be needed. - Page 19 FPGA Registers MISCSR2 – Miscellaneous Control Register #2 This is a register in the always-on power well of the FPGA. It holds its state during sleep modes and can only be reset by a power cycle. It is primarily used for control signals for the always- powered Ethernet controllers and the USB hubs.
- Page 20 FPGA Registers Table 10: MISCSR2 – Misc. Control Register #2 Identifier Access Default Description USB_HUBMODE Determines whether the hub resets only once (to support wake-up from sleep modes on USB ports) or resets every time it enters sleep modes using the platform reset: 0 –...
- Page 21 FPGA Registers Identifier Access Default Description Disable control for the paddleboard USB 2.0 ports 0,1 VBUS power switches (there are two power-switches but they have a common power enable and overcurrent status) 0 – VBUS power switches are enabled USB2_DIS1 1 –...
- Page 22 FPGA Registers MISCSR4 – Miscellaneous Control Register #4 This register is used to monitor the overcurrent status of the 2x USB 3.0 VBUS power switch. Table 12: MISCSR4 – Misc. Control Register #4 Bits Identifier Access Default Description RESERVED Reserved – Writes are ignored. Reads always return 0 RESERVED Reserved –...
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Page 23: Spi Control Registers
FPGA Registers SPI C ONTROL EGISTERS These are placed at the traditional offset 0x8 location. Only external SPX interface devices use this interface. Because the board uses a 9-pin SPX connector, only two devices are supported. SPICONTROL Table 13: SPI Interface Control Register Acces Default Identifier... - Page 24 FPGA Registers SPISTATUS The SPX interrupt is not connected on this product. The control bits and status associated are still defined in the register set but the SPX interrupt will always be de-asserted. Table 14: SPI Interface Status Register Bits Identifier Access Default...
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Page 25: Spi Data Registers
FPGA Registers SPI D EGISTERS There are four data registers used on the SPI interface. How many are used depends on the device being communicated with. SPIDATA0 is typically the least significant byte and SPIDATA3 is the most significant byte. Any write to the most significant byte SPIDATA3 initiates the SCLK and, depending on the MAN_SS state, will assert a slave select to begin an SPI bus transaction. -
Page 26: Spi Debug Control Register And Msata/Pcie Select Control Register
FPGA Registers SPI D SATA/PCI EBUG ONTROL EGISTER AND M ELECT ONTROL EGISTER This register is only used to set an SPI loopback (debug/test only) but is also used for the mSATA/PCIe Minicard Mux select. Table 15: SPI – SPI Debug Control Register Identifier Access Default... - Page 27 FPGA Registers Identifier Access Default Description IRQSEL(2:0) ADC ALARM Interrupt IRQ Select in LPC SERIRQ: 000 – IRQ3 001 – IRQ4 010 – IRQ5 011 – IRQ10 100 – IRQ6 101 – IRQ7 110 – IRQ9 111 – IRQ11 FYI – same values are other products. ADC_RESET ADS8668A ADC RESET 0 –...
- Page 28 FPGA Registers DIOPOLx (x=1,2) – Digital I/O Polarity Control Registers These two registers control the polarity of the 16 Digital I/O signals. This reset depends on the state of the FPGA_PSEN signal. If FPGA_PSEN is a ‘0’ then the reset is the power-on and Platform Reset.
- Page 29 FPGA Registers Table 22: DIOIN1 – Digital I/O 8-1 Input Status Register Bits Identifier Access Default Description Reads the DIO input status. For each bit: 0 – Input de-asserted if polarity not-inverted; IN_DIO[8:1] asserted if polarity inverted Input asserted if polarity not-inverted; de-asserted if polarity inverted Table 23: DIOIN2 –...
- Page 30 FPGA Registers Table 27: DIOISTAT2 – Digital I/O 16-9 Interrupt Mask Register Bits Identifier Access Default Description DIOx interrupt status. A read returns the interrupt status. Writing a ‘1’ clears the interrupt status. RW/C ISTAT_DIO[16:9] This bit is set to a ‘1’ on a transition from low-to-high (POL_DIOx=0) or high-to-low (POL_DIOx=1).
- Page 31 FPGA Registers AUXDIR – AUX GPIO Direction Control Register This register controls the direction of the eight AUX GPIO signals. This reset depends on the state of the FPGA_PSEN signal. If FPGA_PSEN is a ‘0’ then the reset is the power-on and Platform Reset. If FPGA_PSEN is a ‘1’ then this register is only reset at power-on.
- Page 32 FPGA Registers Table 31: AUXOUT – AUX GPIO Output Control Register Bits Identifier Access Default Description Sets the AUX GPIOx output values. For each bit: 0 – De-asserts the output (0 if polarity not-inverted, 1 if inverted) OUT_GPIO[8:1] 1 – Asserts the output (1 if polarity not-inverted, 0 if inverted) AUXIN –...
- Page 33 FPGA Registers AUXMODE1– AUX I/O Mode Register #1 These two registers select the mode on each AUX GPIO. This reset depends on the state of the FPGA_PSEN signal. If FPGA_PSEN is a ‘0’ then the reset is the power-on and Platform Reset. ...
- Page 34 FPGA Registers WDT_CTL – Watchdog Control Register Reset type is Platform. Table 36: WDT_CTL – Watchdog Control Register Bits Identifier Access Default Description Watchdog interrupt enable/disable: IRQEN 0 – Interrupts disabled 1 – Interrupts enabled Watchdog interrupt IRQ select in LPC SERIRQ: 000 –...
- Page 35 FPGA Registers WDT_VAL – Watchdog Value Register This register sets the number of seconds for a Watchdog prior to enabling the watchdog. By writing this value, the watchdog can be prevented from “firing”. A watchdog fires whenever this registers value is all 0s, so it must be set to a non-zero value before enabling the watchdog to prevent an immediate “firing”.
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Page 36: Fancon - Fan Control Register
FPGA Registers AUXMODE2– AUX I/O Mode Register #2 This register defines the interrupt mapping for the AUX GPIOs. Reset type is Platform. Table 39: AUXMODE2 - AUX I/O Mode Register #2 Bits Identifier Access Default Description AUX GPIO interrupt enable/disable: IRQEN 0 –... -
Page 37: Fantachls, Fantachms - Fantach Status Registers
FPGA Registers Table 40: FANCON – Fan Control Register Bits Identifier Access Default Description Selects the COM Module fan control instead of the FPGA. 0 – FPGA controls fan on/off. 1 – COM Module controls fan on/off (or PWM if used) . COM_MODE Note: COM Module will only operate with 4-wire fans if using PWM speed control. - Page 38 FPGA Registers Table 41: FANTACHLS – FANTACH Status Register LS Bits Bits Identifier Access Default Description LS 8-bits of FANTACH (read this first since it latches the value for FANTACH[7:0] the MS 8 bits) Table 42: FANTACHMS – FANTACH Status Register MS Bits Bits Identifier Access...
- Page 39 FPGA Registers UART1CR – UART1 Control Register (COM1) Reset type is Platform. Note: The BIOS (via ACPI) may modify this register when in an ACPI-capable operating system. The register can be read for status purposes but do not write to it unless you are using a non-ACPI operating system.
- Page 40 FPGA Registers UART2CR – UART2 Control Register (COM2) Reset type is Platform. Table 44: UART2CR – UART2 Control Register (COM2) Bits Identifier Access Default Description UART interrupt enable/disable: IRQEN 0 – Interrupts disabled 1 – Interrupts enabled UART interrupt IRQ select in LPC SERIRQ: 000 –...
- Page 41 FPGA Registers UART3CR – UART3 Control Register (COM3) Reset type is Platform. Table 45: UART3CR – UART3 Control Register (COM3) Bits Identifier Access Default Description UART interrupt enable/disable: IRQEN 0 – Interrupts disabled 1 – Interrupts enabled UART interrupt IRQ select in LPC SERIRQ: 000 –...
- Page 42 FPGA Registers UART4CR – UART4 Control Register (COM4) Reset type is Platform. Table 46: UART4CR – UART4 Control Register (COM4) Bits Identifier Access Default Description UART interrupt enable/disable: IRQEN 0 – Interrupts disabled 1 – Interrupts enabled UART interrupt IRQ select in LPC SERIRQ: 000 –...
- Page 43 FPGA Registers UARTMODE1 – UART MODE REGISTER #1 When the COM Transceiver Mode is set to RS422/485 (in the XCVRMODE register) and the RS-485 Automatic Direction Control is enabled (e.g., UART1_485ADC set to ‘1’) then the transceiver Tx output is enabled. When there are bytes to transmit and the transceiver Tx output is disabled (i.e., tri-stated) when there are no bytes to transmit.
- Page 44 FPGA Registers Table 47: UARTMODE1 – UART MODE Register #1 Bits Identifier Access Default Description COM4 RS-485 Automatic Direction Control: 0 – Disabled UART4_485ADC 1 – Enabled Note: Only enable in RS-485 mode. The COM4_MODE in XCVRMODE register must also be set to a ’1’ COM3 RS-485 Automatic Direction Control: 0 –...
- Page 45 FPGA Registers UARTMODE2 – UART MODE REGISTER #2 Standard software (the BIOS and the operating system) assumes the baud-rate clock is 1.8432 MHz and programs the divisors accordingly; however, a faster oscillator is needed for baud rates higher than 115,200. The FAST_MODE bit in this register shifts the divisor by 4 bits (multiply by 16) so that the legacy baud rate comes out correctly for the 16x UART clock.
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Page 46: Programming Information For Hardware Interfaces
Connect the cathode of the LED to J2, pin 16; connect the anode to +3.3 V. An on-board resistor limits the current when the circuit is turned on. A programmable LED is provided on the CBR-4005B paddleboard. Refer to the VL-EPU-4562 Hardware Reference Manual for the location of the Programmable LED on the CBR-4005B paddleboard. -
Page 47: Processor Wake# Capabilities
Programming Information for Hardware Interfaces Processor WAKE# Capabilities The following devices can wake up the processor using the PCIE_WAKE# signal to the CPU module: I210 Ethernet controller Minicard #1 WAKE# signal Minicard #2 WAKE# signal FPGA via a secondary function on one of the 8x GPIOs The following USB devices can wake up the processor using the in-band SUSPEND protocol: ...