Spi Registers - VersaLogic Iguana VL-EPIC-25 Reference Manual

SPI R
EGISTERS
A set of control and data registers are available for SPI transactions. The following tables
describe the SPI control registers (SPICONTROL and SPISTATUS) and data registers
(SPIDATA3-0).
SPICONTROL (READ/WRITE) CA8h
D7
CPOL
Bit Mnemonic
D7 CPOL
D6 CPHA
D5-D4 SPILEN
D3 MAN_SS
D2-D0 SS
VL-EPIC-25 Reference Manual
D6 D5
CPHA SPILEN1 SPILEN0
Table 22: SPI Control Register 1 Bit Assignments
Description
SPI Clock Polarity – Sets the SCLK idle state.
0 = SCLK idles low
1 = SCLK idles high
SPI Clock Phase – Sets the SCLK edge on which valid data will be
read.
0 = Data read on rising edge
1 = Data read on falling edge
SPI Frame Length – Sets the SPI frame length. This selection works in
manual and auto slave select modes.
SPILEN1 SPILEN0
0 0
0 1
1 0
1 1
SPI Manual Slave Select Mode – This bit determines whether the
slave select lines are controlled through the user software or are
automatically controlled by a write operation to SPIDATA3 (CADh). If
MAN_SS = 0, then the slave select operates automatically; if MAN_SS
= 1, then the slave select line is controlled manually through
SPICONTROL bits SS2, SS1, and SS0.
0 = Automatic, default
1 = Manual
SPI Slave Select – These bits select which slave select will be asserted. The
SSx# pin on the baseboard will be directly controlled by these bits when
MAN_SS = 1.
SS2 SS1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
D4 D3 D2
MAN_SS SS2
Frame Length
8-bit
16-bit
24-bit
32-bit
SS0 Slave Select
0 None, port disabled
1 SPX Slave Select 0, J27 pin-8
0 SPX Slave Select 1, J27 pin-9
1 SPX Slave Select 2, J27 pin-10
0 SPX Slave Select 3, J27 pin-11
1 A/D Converter (on-board)
0 Digital I/O (on-board)
1 D/A Converter (on-board)
Interfaces and Connectors
D1 D0
SS1 SS0
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