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Summary of Contents for VersaLogic Iguana VL-EPIC-25
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Page 1: Reference Manual
Reference Manual DOC. REV. 12/6/2013 Iguana (VL-EPIC-25) Intel® Atom-based SBC with Ethernet, SATA, USB, eUSB, CompactFlash, mSATA, Serial, Industrial I/O, and SPX™... - Page 2 Copyright © 2013 VersaLogic Corp. All rights reserved. Notice: Although every effort has been made to ensure this document is error-free, VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose.
- Page 3 Product Revision Notes – Commercial release. Revsion 1.00 Support The Iguana support page, at http://www.versalogic.com/private/iguanasupport.asp, contains additional information and resources for this product including: Reference Manual (PDF format) Device drivers Data sheets and manufacturers’ links for chips used in this product ...
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Page 4: Table Of Contents
Contents Introduction ........................1 Description .......................... 1 Features and Construction ..................1 Technical Specifications ..................... 2 Block Diagram ........................3 Thermal Considerations ...................... 4 CPU Die Temperature ................... 4 Model Differences ....................4 RoHS Compliance ......................5 About RoHS ......................5 Warnings .......................... - Page 5 Contents Power Requirements .................... 22 Power Delivery Considerations ................23 Lithium Battery ....................23 CPU ........................... 24 System RAM ........................25 Clearing Non-volatile RAM (NVRAM) ................25 Real-Time Clock (RTC) ....................25 Setting the Clock....................25 Clearing the Real-Time Clock ................26 Console Redirection ......................
- Page 6 Analog Input Using the SPI Interface ..............47 Analog Output ........................49 Counter / Timers ....................... 50 SPX ........................... 51 VersaLogic SPX Expansion Modules ..............52 SPI Registers ......................53 System Resources and Maps ..................56 Legacy Memory Map ......................56 I/O Map ..........................
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Page 7: Introduction
Card/mSATA SSD, CompactFlash The Iguana is compatible with popular operating systems such as Windows CE, Windows XP Professional/XP Embedded (SP3), Linux, VxWorks, and QNX (see the VersaLogic OS Compatibility Chart). Note: Windows 7 will not install with less than 512 MB RAM. -
Page 8: Technical Specifications
Introduction Technical Specifications Specifications are typical at 25°C with +5V supply unless otherwise noted. Specifications are subject to change without notification. Board Size: Serial Ports 0-1: 4.5" x 6.5" (EPIC standard) RS-232/422/485, 16C550 compatible, 460 Kbps max., 4-wire RS-232 (CTS and RTS Storage Temperature: handshaking), DB-9 connector on VL-CBR-5013 -40°... -
Page 9: Block Diagram
Introduction Block Diagram Regulators Power Key: On-Board Peripheral Includes Power Mgt & Input Sequencing Logic LVDS 18-bit LVDS DDR3 DDR3 Panel SO-DIMM Intel Atom Processor D425 (1 core) CK505 Clock D525 (2 core) Generation 4xDMI Gen 1 Electronic Mux (FSB) SATA 2 E-Mux PCIe x1 [6]... -
Page 10: Thermal Considerations
ODEL IFFERENCES VersaLogic offers both commercial and industrial temperature models of the VL-EPIC-25. The basic operating temperature specification for both models is shown below. VL-EPIC-25SA and SB: 0°C to +60°C free air, no airflow, heatsink, no fan ... -
Page 11: Rohs Compliance
(PBDE) flame retardants, in certain electrical and electronic products sold in the European Union (EU) beginning July 1, 2006. VersaLogic Corp. is committed to supporting customers with high-quality products and services meeting the European Union’s RoHS directive. -
Page 12: Handling Care
Click the link below to see all KnowledgeBase articles related to the VL-EPIC-25. VersaTech KnowledgeBase If you have further questions, contact VersaLogic Technical Support at (503) 747-2261. VersaLogic support engineers are also available via e-mail at Support@VersaLogic.com. EPAIR... - Page 13 Introduction Non-warranty Repair All approved non-warranty repairs are subject to diagnosis and labor charges, parts charges, and return shipping fees. Please specify the shipping method you prefer and provide a purchase order number for invoicing the repair. Note: Please mark the RMA number clearly on the outside of the box before returning.
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Page 14: Configuration And Setup
USB keyboard and mouse SATA hard drive USB CD-ROM drive LVDS or VGA display The following VersaLogic cables are recommended: VL-CBR-2022 – Power adapter cable VL-CBR-5013 – Paddleboard VL-CBR-0701 – SATA data cable ... - Page 15 Configuration and Setup USB Keyboard VL-CBR-5013B and USB Mouse VL-CBR-5013A USB CD- ROM Drive OS Installation VL-CBR-0701 CD-ROM IGUANA SATA VL-EPIC-25 Hard Drive VL-CBR-0401 VL-CBR-2022 Power Supply SVGA VL-CBR-2010 or VL-CBR-2011 LVDS SVGA or LVDS VL-CBR-1201 Figure 1. Typical Start-up Configuration 1.
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Page 16: Operating System Installation
The standard PC architecture used on the Iguana makes the installation and use of most of the standard x86-based operating systems very simple. The operating systems listed on the VersaLogic OS Compatibility Chart use the standard installation procedures provided by the maker of the OS. -
Page 17: Physical Details
Physical Details Dimensions and Mounting GUANA IMENSIONS The VL-EPIC-25 complies with EPIC dimensional standards. Dimensions are given below to help with pre-production planning and layout. 6.096 5.596 5.496 2.596 2.446 0.000 -0.200 Figure 2. Iguana Dimensions and Mounting Holes (Not to scale. All dimensions in inches.) VL-EPIC-25 Reference Manual... -
Page 18: Vl-Cbr-5013 Dimensions
Physical Details VL-CBR-5013 D IMENSIONS 5.50 5.10 1.57 1.17 1.95 1.24 0.065 Figure 3. VL-CBR-5013 Dimensions and Mounting Holes (Not to scale. All dimensions in inches.) VL-EPIC-25 Reference Manual... -
Page 19: Vl-Cbr-4004 Dimensions
Physical Details VL-CBR-4004 D IMENSIONS 2.87 0.25 0.25 2.38 0.70 1.95 0.63 0.62 0.06 0.40 Figure 4. VL-CBR-4004 Dimensions and Mounting Holes (Not to scale. All dimensions in inches.) VL-EPIC-25 Reference Manual... -
Page 20: Hardware Assembly
Physical Details ARDWARE SSEMBLY The Iguana uses PC/104 and PC/104-Plus connectors so that expansion modules can be added to the top of the stack. PC/104 (ISA) modules must not be positioned between the Iguana and any PC/104-Plus (PCI) modules on the stack. The entire assembly can sit on a table top or be secured to a base plate. -
Page 21: External Connectors
Physical Details External Connectors – T GUANA ONNECTOR OCATIONS J25 – Digital, Analog, Timers J19 – User I/O J27 - SPX Ethernet 1 Ethernet 0 External Ethernet LED eUSB J16 J17 J16 - USB0 J17 - USB1 J11 - SATA0 J12 - SATA1 J11 J12 PCIe Mini Card... -
Page 22: Iguana Connector Locations - Bottom
Physical Details – B GUANA ONNECTOR OCATIONS OTTOM CompactFlash SODIMM Figure 7. Connector Locations (Bottom) VL-EPIC-25 Reference Manual... -
Page 23: Iguana Connector Functions And Interface Cables
Physical Details GUANA ONNECTOR UNCTIONS AND NTERFACE ABLES Table 1 provides information about the function, mating connectors, and transition cables for Iguana connectors. Page numbers indicate where a detailed pinout or further information is available. Table 1: Connector Functions and Interface Cables Pin 1 Location Mating Transition... -
Page 24: Vl-Cbr-5013 Connector Locations
Physical Details VL-CBR-5013 C ONNECTOR OCATIONS Speaker Paddleboard Adapter Ext. Pushbutton COM2 Controls COM0 (Top) USB3 (Top) USB1 (Top) Audio Power Reset COM3 COM1 USB4 USB2 In (Top) (Bottom) (Bottom) (Bottom) Out (Bottom) Programmable LED (Top) Power LED (Bottom) Figure 8. VL-CBR-5013 Connector Locations VL-CBR-5013 C ONNECTOR UNCTIONS... -
Page 25: Vl-Cbr-4004 Connector Locations
Physical Details VL-CBR-4004 C ONNECTOR OCATIONS = Pin 1 Figure 9. VL-CBR-4004 Connectors VL-EPIC-25 Reference Manual... -
Page 26: Jumper Blocks
Physical Details Jumper Blocks UMPERS HIPPED ONFIGURATION Figure 10. Jumper Block Locations VL-EPIC-25 Reference Manual... -
Page 27: Jumper Summary
Physical Details UMPER UMMARY Table 3: Jumper Summary Jumper Description Block Shipped Page — V1[1-2-3] V1[1-2] In Factory Use Only. Jumper may be installed or removed. V2[1-2] SPI Flash Write-Protect In – Writable Out – Write Protected Real-Time Clock (RTC) Reset V3[1-2-3] [1-2] In [1-2] In –... -
Page 28: System Features
System Features Power Supply OWER ONNECTORS Main power is applied to the Iguana through an EPIC-style 10-pin polarized connector at location J29. Warning! To prevent severe and possibly irreparable damage to the system, it is critical that the power connectors are wired correctly. Make sure to use both +5VDC pins and all ground pins to prevent excess voltage drop. -
Page 29: Power Delivery Considerations
ELIVERY ONSIDERATIONS Using the VersaLogic approved power supply (VL-PS200-ATX) and power cable (VL-CBR- 2022) will ensure high quality power delivery to the board. Customers who design their own power delivery methods should take into consideration the guidelines below to ensure good power connections. -
Page 30: Cpu
System Features Figure 11. Battery Life vs. Storage Temperature Intel® Atom™ D425 and D525 processors include the following key features: On die, primary 32-kB instructions cache and 24-kB write-back data cache Intel® Hyper-Threading Technology 2-threads per core On die 2 x 512-kB, 8-way L2 cache for D500 dual-core processor, 1 x 512-kB, 8-way L2 cache for D400 single-core processor Processor memory features include:... -
Page 31: System Ram
System Features System RAM The Iguana accepts one 204-pin DDR3 SO-DIMM memory module with the following characteristics: Size Up to 2GB (1GB or 2GB recommended) Voltage +1.5V Type DDR3, 800 MT/s (400 MHz clock) Clearing Non-volatile RAM (NVRAM) You can clear NVRAM and reset the BIOS settings to factory defaults by following the instructions below. -
Page 32: Clearing The Real-Time Clock
System Features LEARING THE LOCK You can move the V3 jumper to position [2-3] for a minimum of two seconds to clear the RTC. When clearing the RTC: 1. Power off the Iguana. 2. Move the jumper from V3[1-2] to V3[2-3] and leave it for two or more seconds. 3. -
Page 33: Interfaces And Connectors
Interfaces and Connectors Expansion Buses Note Some information in this section may change as the BIOS continues in development. PC/104-P (PCI + ISA) PCI-104 (PCI O PC/104-Plus and PCI-104 modules can be secured directly to the top of the Iguana. Make sure to correctly configure the slot position jumpers on each PC/104-Plus module appropriately. -
Page 34: Pc/104 I/O Support
Next the PCI devices are assigned IRQs. After an OS loads and transitions from 8259 to APIC mode, these PCI IRQs will be freed and available for legacy use. In the 1.00 BIOS, VersaLogic recommends IRQ6 for ISA bus use in a OS using the legacy 8259 interrupt controller. -
Page 35: Ethernet Interface
Interfaces and Connectors Ethernet Interface The Iguana features two on-board Intel 82574IT Gigabit Ethernet controllers. The controllers provide a standard IEEE 802.3 Ethernet interface for 1000Base-T, 100Base-TX, and 10Base-T applications. RJ45 connectors are located at locations J22 (Ethernet 1) and J20 (Ethernet 0). While these controllers are not NE2000-compatible, they are widely supported. -
Page 36: Status Led
Interfaces and Connectors TATUS Connector J28 provides an additional on-board Ethernet status LED interface. The +3.3V power supplied to this connector is protected by a 1 Amp fuse. Table 7: Ethernet Status LED Pinout Signal On-Board LED Name Function Equivalent —... -
Page 37: Serial Ports
Interfaces and Connectors Serial Ports The Iguana features four on-board 16550-based serial communications channels located at standard PC I/O addresses. All serial ports can be operated in RS-232 4-wire, RS-422, or RS-485 modes. IRQ lines are chosen in BIOS setup. Each COM port can be independently enabled, disabled, or assigned a different I/O base address in BIOS setup. -
Page 38: Serial Port Connectors
Interfaces and Connectors ERIAL ONNECTORS The pinouts of the DB9M connectors apply to the serial connectors on the VersaLogic breakout board VL-CBR-5013. These connectors use IEC 61000-4-2-rated TVS components to help protect against ESD damage. Table 9: COM0-1 Pinout – VL-CBR-5013 Connector J2... -
Page 39: Flash Interfaces
CF port. USB S OCKET The Iguana includes an eUSB port. The VersaLogic VL-F15 Series of eUSB SSD modules are available in sizes of 2 GB or 4 GB. Contact VersaLogic Sales to order. eUSB modules are secured to the on-board standoff using M2.5 x 6mm pan head Philips nylon screws. - Page 40 To secure a Mini Card or mSATA module to the on-board standoffs, use two M2.5 x 6mm pan head Philips nylon screws. These screws are available in quantities of 10 in the VL-HDW-108 hardware kit from VersaLogic. Table 12: PCIe Mini Card / mSATA Pinout...
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Page 41: Pcie Mini Card Wireless Status Leds
Some PCIe modules use this signal as a second Mini Card wireless disable input. On the Iguana, this signal is available for use for mSATA versus PCIe Mini Card detection. There is an option on the VersaLogic Features BIOS setup screen for setting the mSATA detection method. IRELESS... -
Page 42: Video
Interfaces and Connectors Video An on-board video controller integrated into the chipset provides high-performance video output for the Iguana. The controller supports dual, simultaneous, independent video output. The Iguana can also be operated without video attached (see Console Redirection). The Iguana supports two types of video output, SVGA and LVDS Flat Panel Display. SVGA O UTPUT ONNECTOR... -
Page 43: Lvds Flat Panel Display Connector
BIOS setup provides several options for standard LVDS flat panel types. If these options do not match the requirements of the panel you are attempting to use, contact Support@VersaLogic.com for a custom video BIOS. Table 14: LVDS Flat Panel Display Pinout... -
Page 44: Audio
Interfaces and Connectors Audio The audio interface on the Iguana is implemented using an Integrated Device Technology, Inc. 92HD87B1X5 Audio Codec. This interface is Intel High Definition Audio compatible. Drivers are available for most Windows-based and Linux operating systems. To obtain the most current versions, consult the Iguana product support page. -
Page 45: User I/O Connector
Interfaces and Connectors User I/O Connector The 50-pin user I/O connector (J19) incorporates the COM ports, four USB ports, programmable LED, power LED, pushbutton reset, power button, audio line in/out, and speaker interfaces. The table below illustrates the function of each pin. Table 16: User I/O Connector Pinout CBR-5013 CBR-5013... -
Page 46: Pushbutton Reset
Interfaces and Connectors Pushbutton Reset Connector J19 includes an input for a pushbutton reset switch. Shorting J19 pin 40 to ground causes the Iguana to reboot. This must be a mechanical switch or an open-collector or open-drain active switch with less than a 0.5V low-level input when the current is 1 mA. There must be no pull-up resistor on this signal. -
Page 47: External Speaker
Interfaces and Connectors External Speaker Connector J19 includes a speaker output signal at pin 39. The VL-CBR-5013 breakout board provides a Piezo electric speaker. LEDs ROGRAMMABLE Connector J19 includes an output signal for a programmable LED. Connect the cathode of the LED to J19 pin 38;... -
Page 48: Digital I/O
Digital I/O 16 4 (IO28) Ground 5 (GND4) Note: Connector J6 pin 5 on the CBR-4004 is labeled "GND3/PBRST#" for compatibility with other VersaLogic CPU boards. When connected to the Iguana, this pin is GND3. I/O P SPI I IGITAL ONFIGURATION... - Page 49 Interfaces and Connectors Digital I/O Interrupt Generation Using the SPI Interface Digital I/O can be configured to issue hardware interrupts on the transition (high to low or low to high) of any digital I/O pin. IRQ assignment is made in SPI control register SPISTATUS. This IRQ is shared among all SPI devices connected to the Iguana (the ADC and DAC devices on the SPI interface do not have interrupts).
- Page 50 Interfaces and Connectors DX, CA8h SPI 6 AL, 26h ;SPICONTROL: SPI Mode 00, 24bit, DX, AL DX, CA9h AL, 30h ;SPISTATUS: 8MHz, no IRQ, left-shift DX, AL DX, CABh AL, 44h ;SPIDATA1: mirror and open-drain interrupts DX, AL DX, CACh AL, 0Ah ;SPIDATA2: MCP23S17 IOCON register address 0Ah DX, AL...
- Page 51 Interfaces and Connectors '================================ 'SPICONTROL1 Register '--------------------------- 'D7 CPOL = 0 SPI Clock Polarity (SCLK idles low) 'D6 CPHA = 0 SPI Clock Phase (Data read on rising edge) 'D5 SPILEN1 = 1 SPI Frame Length (24-Bit) 'D4 SPILEN0 " "...
- Page 52 Interfaces and Connectors 'INITIALIZE DIRECTION OF DIO LINES D15-D8 AS INPUTS '================================================== 'Direction = All Inputs OUT SPIDATA1, &HFF 'MCP23S17 IODIRA Register Address OUT SPIDATA2, &H0 'MCP23S17 SPI Control Byte (Write) OUT SPIDATA3, &H40 WHILE (INP(SPISTATUS) AND &H1) = &H1: WEND 'Repeat until ESC key is pressed WHILE INKEY$ <>...
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Page 53: Analog Input
Interfaces and Connectors Analog Input The Iguana uses a multi-range, 12-bit Linear Technology LTC1857 A/D converter with eight single-ended input signals (even and odd analog channels, for example inputs 1 and 2, can also be combined as differential inputs). The converter has a 100 kilo-samples-per-second (Ksps) sampling rate, with a 4 µs acquisition time, with per-channel input ranges of 0 to +5V or 0 to +10V unipolar, and ±5V or ±10V bipolar The Iguana A/D converter is controlled using the SPI registers. - Page 54 Interfaces and Connectors Initiating an Analog Conversion Using the SPI Interface The following procedure can be used to initiate an analog conversion using the SPI interface. 1. Write 15h to the SPICONTROL register (I/O address CA8h) – This value configures the SPI port to select the on-board A/D converter, 16-bit frame length, low SCLK idle state, rising edge SCLK edge, and automatic slave select.
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Page 55: Analog Output
Interfaces and Connectors Analog Output The Iguana uses a 12-bit Linear Technology LTC2634 D/A converter with four (4) single-ended output signals. The converter has 5 µs per-channel update rate with a 0 to 4.096V output voltage range. The Iguana D/A converter is controlled using the SPI registers. The D/A converter is accessed via SPI slave select 7 (writing 7h to the SS field in SPICONTROL). -
Page 56: Counter / Timers
Interfaces and Connectors Counter / Timers The Iguana includes two uncommitted 8254 type counter/timer channels for general program use. External control signals for the two channels are available on connector J25. Table 20: Counter Timer Pinout Signal Signal VL-CBR-4004 VL-CBR-4004 Direction* Name Function... -
Page 57: Spx
Interfaces and Connectors Up to four serial peripheral expansion (SPX) devices can be attached to the Iguana at connector J27 using the VL-CBR-1401 or VL-CBR-1402 cable. The SPX interface provides the standard serial peripheral interface (SPI) signals: SCLK, MISO, and MOSI, as well as four chip selects, SS0# to SS3#, and an interrupt input, SINT#. -
Page 58: Versalogic Spx Expansion Modules
XPANSION ODULES VersaLogic offers a number of SPX modules that provide a variety of standard functions, such as analog input, digital I/O, CANbus controller, and others. These are small boards (1.2” x 3.78”) that can mount on the PC/104 stack, using standard standoffs, or up to two feet away from the info@VersaLogic.com... -
Page 59: Spi Registers
Interfaces and Connectors SPI R EGISTERS A set of control and data registers are available for SPI transactions. The following tables describe the SPI control registers (SPICONTROL and SPISTATUS) and data registers (SPIDATA3-0). SPICONTROL (READ/WRITE) CA8h CPOL CPHA SPILEN1 SPILEN0 MAN_SS Table 22: SPI Control Register 1 Bit Assignments Mnemonic... - Page 60 Interfaces and Connectors SPISTATUS (READ/WRITE) CA9h IRQSEL1 IRQSEL0 SPICLK1 SPICLK0 HW_IRQ_EN LSBIT_1ST HW_INT BUSY Table 23: SPI Control Register 2 Bit assignments Mnemonic Description IRQ Select – These bits select which IRQ will be asserted when a D7-D6 IRQSEL hardware interrupt from a connected SPI device occurs. The HW_IRQ_EN bit must be set to enable SPI IRQ functionality.
- Page 61 Interfaces and Connectors SPIDATA0 (READ/WRITE) CAAh MSbit LSbit SPIDATA1 (READ/WRITE) CABh MSbit LSbit SPIDATA2 (READ/WRITE) CACh MSbit LSbit SPIDATA3 (READ/WRITE) CADh MSbit LSbit SPIDATA3 contains the most significant byte (MSB) of the SPI data word. A write to this register will initiate the SPI clock and, if the MAN_SS bit = 0, will also assert a slave select to begin an SPI bus transaction.
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Page 62: System Resources And Maps
System Resources and Maps Legacy Memory Map The lower 1 MB memory map of the Iguana is arranged as shown in the following table. Various blocks of memory space between A0000h and FFFFFh are shadowed. Table 24: Memory Map Start Address Address Comment... -
Page 63: Special Registers
Special Registers PLED and Product Code Register PLEDPC (Read/Write) CA0h PLED Table 26: PLED and Product Code Register Bit Assignments Mnemonic Description Light Emitting Diode — Controls the programmable LED on connector J7. PLED 0 = Turns LED off 1 = Turns LED on Product Code —... -
Page 64: Pld Revision And Type Register
Interfaces and Connectors PLD Revision and Type Register REVTYP (Read Only) CA1h PLD4 PLD3 PLD2 PLD1 PLD0 TEMP CUSTOM BETA This register is used to indicate the revision level of the Iguana. Table 27: Revision and Type Register Bit Assignments Mnemonic Description PLD Code Revision Level —... -
Page 65: Bios And Jumper Status Register
Special Registers BIOS and Jumper Status Register BIOSJSR (Read/Write) CA2h BIOS_JMP BIOS_OR BIOS_SEL Reserved Reserved Reserved Reserved GPI_JMP Table 28: Special Control Register Bit Assignments Mnemonic Description System BIOS Selector Jumper Status — Indicates the status of the system BIOS_JMP BIOS selector jumper at V5[1-2]. -
Page 66: Appendix A - References
Appendix A – References Intel Atom D425/D525 Dual Core Intel Atom Datasheet Vol. 1 Vol. 2 Chipset Intel ICH8 Intel ICH8 Datasheet Super I/O Chip SMSC SCH3114 SCH3114 Datasheet Ethernet Controller Intel 82574IT Ethernet Controller Intel 8257IT Datasheet PC/104 Interface PC/104 Specification PC/104-Plus Interface PC/104-Plus Specification... -
Page 67: Appendix B - Custom Programming
Appendix B – Custom Programming PLD Interrupts The PLD can generate interrupts for the internal 8254 timers and the external SPI interrupt (which includes the DIO device interrupt). The SPI interrupt settings are discussed in the section on “SPX Expansion Bus.” This section covers the interrupt settings for the 8254 timers. NTERRUPT ONTROL EGISTER... -
Page 68: Interrupt Status Register
Special Registers NTERRUPT TATUS EGISTER This register is used for reading the status of interrupts generated by the PLD. IRQSTAT (Read-Status/Write-Clear) CA4h Reserved Reserved Reserved Reserved Reserved ISTAT_TC5 ISTAT_TC4 ISTAT_TC3 Table 30: Interrupt Status Register Bit Assignments Mnemonic Description D7-D3 Reserved These bits are reserved. -
Page 69: 8254 Timer Control Register
Special Registers 8254 Timer Control Register This register is used to set modes related to the inputs on the 8254 Timers. TIMCNTRL (Read/Write) CA5h TIM5GATE TIM4GATE TIM3GATE TM4MODE TM4SEL TM3SEL Reserved Reserved Table 31: 8254 Timer Control Register Bit Assignments Mnemonic Description TIM5GATE... -
Page 70: A/D And D/A Control/Status Register
Special Registers The 32-bit cascade mode is set in TM4MODE in the Timer Control Register. There are also internal or external clock selections for the timers in this register using the external clocks ICTC3 and ICTC4 signals on the connector at J25. The internal clock is the PCI clock divided by 8 (33.33 MHz / 8 = 4.167 MHz).
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