Analog Control Register - VersaLogic VSBC-8 Reference Manual

Pentium iii/celeron based sbc with ethernet, video, audio and industrial i/o
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A
C
NALOG
ONTROL
ACR (WRITE) 00E4h (or 1E4h via CMOS Setup)
D7
PD1
Bit
Mnemonic
D7, D6
PD1, PD0
D5
ACQMOD
D4, D3
RNG, BIP
D2-D0
A2, A1, A0
VSBC-8 Reference Manual
R
EGISTER
D6
D5
D4
PD0
ACQMOD
RNG
Table 17: Analog Control Register Bit Assignments
Description
Clock and Power-Down Selection — These bits select the power savings
mode and clock source for the A/D circuit.
PD1
PD0
0
0
0
1
1
0
1
1
Note! STBYPD and FULLPD selections do not affect the clock mode.
Acquisition Mode — This bit selects the type of acquisition mode.
ACQMOD = 0
Internal Acquisition. A write to the ACR register will initiate
an acquisition interval whose duration is internally timed. Conversion starts
when this six-clock-cycle acquisition interval (3.26µs) ends.
ACQMOD = 1
External Acquisition. Use this mode for precise control of the
sampling aperture and/or independent control of acquisition and conversion
times. The acquisition and start-of-conversion is controlled with two separate
writes to the ACR register. The first write, written with ACQMOD = 1, starts
and acquisition interval of indeterminate length. The second write, written with
ACQMOD = 0, terminates acquisition and starts conversion. However, if the
second write contains ACQMOD = 1, an indefinite acquisition interval is
restarted.
Note! The address bits for the input mux (A0–A2) must have the same values on the
first and second write pulses. Power-down mode bits (PD0, PD1) can assume new
values on the second write.
Range and Polarity Selection — These bits select the input range and
polarity on a channel-by-channel basis.
RNG
BIP
0
0
1
0
0
1
1
1
Warning! The board can be damaged if voltages in excess of ±16V are applied.
Input Channel Address — These bits select which input channel you wish to
convert.
A2
A1
A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
D3
D2
BIP
A2
Mode
Normal Operation / External Clock Mode
Normal Operation / Internal Clock Mode
Standby Power-Down (STBYPD)
Full Power-Down (FULLPD)
Input Range
0 to +5V
0 to +10V
±5V
±10V
Channel
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Analog Input
D1
D0
A1
A0
Reference – 35

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