Table 8: Tcr - 8254 Timer Control Register - VersaLogic Osprey Programmer's Reference Manual

Bit Identifier
7 TMR5GATE
6 TMR4GATE
5 TMR3GATE
4 TM45MODE
3 TM4CLKSEL
2 TM3CLKSEL
1 TMROCTST
0 TMRFULL
EPU-3311 Programmer's Reference Manual
Table 8: TCR – 8254 Timer Control Register
Access Default
Debug/Test Only: Controls the "gate" signal on 8254 timer #5 when not
using an external gate signal:
0 – Gate on signal GCTC5 is disabled
R/W
0 1 – Gate on signal GCTC5 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is '0' and then it should be set to '1' and not changed unless using
internal clocking.
Controls the "gate" signal on 8254 timer #4 when not using an external
gate signal:
0 – Gate on signal GCTC4 is disabled
R/W
0 1 – Gate on signal GCTC4 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is '0' and then it should be set to '1' and not changed unless using
internal clocking
Controls the "gate" signal on 8254 timer #3 when not using an external
gate signal:
0 – Gate on signal GCTC3 is disabled
R/W
0 1 – Gate on signal GCTC3 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is '0' and then it should be set to '1' and not changed unless using
internal clocking
Mode to set timers #4 and #5 in:
0 – Timer #4 and #5 form one 32-bit timer controlled by timer #1 signals
1 – Timer #4 and Timer #5 are separate 16-bit timers with their own
R/W
0
control signals.
Almost always used in 32-bit mode especially when TMRFULL is a '0'
(the 16-bit timer #5 if of limited use)
Timer #4 Clock Select:
0 – Use internal 4.125 MHz clock (derived from LPC clock)
R/W
0
1 – Use external ICTC4 assigned to digital I/O
Timer #5 is always on internal clock if configured as a 16-bit clock
Timer #3 Clock Select:
R/W
0
0 – Use internal 4.125 MHz clock (derived from LPC clock)
1 – Use external ICTC3 assigned to digital I/O
Debug/Test Only: Used to derive OCTCx outputs with TIMxGATE
signals for continuity testing only:
R/W
0 0 – Normal operation
1 – Drive OCTCx outputs with corresponding TMRxGATE control
registers (for example, OCTC4 with TMR4GATE) for continuity testing.
R/W
0 This bit can be read or written to, but it has no function.
FPGA Registers
Description
10