Pld Revision And Type Register - VersaLogic Iguana VL-EPIC-25 Reference Manual

PLD Revision and Type Register

REVTYP (Read Only) CA1h
D7
PLD4
This register is used to indicate the revision level of the Iguana.
Bit Mnemonic
D7-D3 PLD
D2 Reserved
D1 CUSTOM
D0 BETA
VL-EPIC-25 Reference Manual
D6 D5
PLD3 PLD2 PLD1
Table 27: Revision and Type Register Bit Assignments
Description
PLD Code Revision Level — These bits are hard-coded and represent the PLD
code revision.
PLD4 PLD3
0 0
0 0
0 0
0 0
0 0
These bits are read-only. Note: For beta boards, the Revision Level is set to 1.00A,
but the Production Level is set to Beta.
This bit is reserved.
PLD Class — This bit indicates whether the PLD code is standard or customized.
0 = Standard PLD code
1 = Custom PLD code
This bit is read-only.
Production Level — This bit indicates if the PLD code is at the beta or production
level.
0 = Production level PLD
1 = Beta level PLD
This bit is read-only.
D4 D3 D2
PLD0 TEMP
PLD2 PLD1 PLD0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
Interfaces and Connectors
D1 D0
CUSTOM BETA
Revision
Rev. 0.10B
Rev. 0.10B
Rev. 0.20A
Rev. 1.00A
Rev. 1.01A
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