Table 11: Tcr - 8254 Timer Control Register - VersaLogic SandCat Programmer's Reference Manual

Table 11: TCR – 8254 Timer Control Register
Bit Identifier
7 TMR5GATE
6 TMR4GATE
5 TMR3GATE
4 TM45MODE
3 TM4CLKSEL
2 TM3CLKSEL
1 RESERVED
0 TMRFULL
EPM-39 Programmer's Reference Manual
Access Default
Debug/Test Only: Controls the "gate" signal on 8254 timer #5 when not
using an external gate signal:
0 – Gate on signal GCTC5 is disabled
R/W
0 1 – Gate on signal GCTC5 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is '0' and then it should be set to '1' and not changed unless using
internal clocking.
Controls the "gate" signal on 8254 timer #4 when not using an external
gate signal:
0 – Gate on signal GCTC4 is disabled
R/W
0 1 – Gate on signal GCTC4 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is '0' and then it should be set to '1' and not changed unless using
internal clocking
Controls the "gate" signal on 8254 timer #3 when not using an external
gate signal:
0 – Gate on signal GCTC3 is disabled
R/W
0 1 – Gate on signal GCTC3 is enabled
Always set to 0 when configuring timer modes except when TMRFULL
is '0' and then it should be set to '1' and not changed unless using
internal clocking
Mode to set timers #4 and #5 in:
0 – Timer #4 and #5 form one 32-bit timer controlled by timer #1 signals
1 – Timer #4 and Timer #5 are separate 16-bit timers with their own
R/W
0
control signals.
Almost always used in 32-bit mode especially when TMRFULL is a '0'
(the 16-bit timer #5 if of limited use)
Timer #4 Clock Select:
0 – Use internal 4.125 MHz clock (derived from PCI clock)
R/W
0
1 – Use external ICTC4
Timer #5 is always on internal clock if configured as a 16-bit clock
Timer #3 Clock Select:
R/W
0
0 – Use internal 4.125 MHz clock (derived from PCI clock)
1 – Use external ICTC3 assigned to Digital I/O
RO
0 Reserved. Writes are ignored; reads always return 0.
DIOs to use for timer signals (TMREN must be a '1' in the DIOCR
register to use the timers).
0 – 4-wire timers and DIO16-DIO13 are external timer control signals
1 – 8-wire and DIO16-DIO9 are external timer control signals
Because the gates-controls are not connected to digital I/Os when
R/W
0
TMRFULL is a '0', the TIMxGATE gate controls in this register are used
so they need to be set to '1' and should not be toggled during operation
with external timers (since there is no continuous clock to synchronize
them to) but can be toggled if using the internal clock. If you need
gating in external modes, set TMRFULL to a '1'.
FPGA Registers
Description
12