1.10 Other Standard Features - Elgar SW 5550AE Operation Manual

SW 5550AE • SW 3700AE • SW 1850AE

1.10 Other Standard Features

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1- to 3-Phase Programmable
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IEEE 488.2 Interface
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SCPI Protocol
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Waveform Trigger Output
(1 MegΩ Load Drive; positive edge is at 0° ±30µs, 0 to 5V logic)
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BNC Outputs for Waveform Viewing
(1 MegΩ Load Drive, 1.25 VRMS = Full Scale)
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SYNC OUT. User programmed for:
Cycle Start, all cycles
Segment Start. all segments
Segment Start, selected segments
For loads ≥2 kΩ: Vout ≤1V Low State; Vout ≥2.4V High State; Negative edge is
at 0° ±30 µs.
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CLOCK/LOCK
CLOCK pulses at programmed frequency for loads ≥2 kΩ. Vout ≤1V Low State;
Vout ≥2.4V High State. Negative edge is at 0° ±30µs.
LOCK locks output to input 'TTL' frequency; signal needs to supply pull down
current of 15 mA with voltage drop of ≤0.6V; no pull up needed. Negative edge
is at 0° ±30 µs.
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PLL Specifications
External PLL input frequency range is 45.00 Hz to 500.00 Hz.
Tracking range is ±10% of programmed PLL center frequency.
External PLL input duty cycle is 50% ±10%.
External PLL input slew rate is .02% of input frequency/second, maximum, which
produces a maximum phase shift of 5° from the external PLL input falling edge to
the output rising edge.
The rising edge of the output will be locked to the falling edge of the external PLL
input and will have less than a 30 µsec propagation delay.
Maximum output jitter when locked is <1% of external PLL input period.
PLL lock is achieved in <5 seconds.
Operation Manual
General Description
1-7