Table 3-3 System External Menu - Elgar SW 5550AE Operation Manual

Operation
SELECTION PURPOSE
Amplitude modulation of an output waveform is possible via an input
EXT MOD
signal from the rear panel. Input of 0-5 Vrms corresponds to a 0-20%
(External
Amplitude modulation. To allow for the modulation voltage, the maximum prog-
rammed voltage is 130 Vrms in low range, and 260 Vrms in high range.
Modulation)
Input on rear panel allows reference signal to go directly to amplifiers.
DIR INPUT
A signal of 0–5 Vrms (±7.07 Vpeak) or ±5VDC corresponds to 0 to full
(External
scale programmed voltage output.
Direct Input)
CAUTION: Do not exceed the maximum frequency specifications
listed in Section 4.
Input on rear panel is used to scale output waveform. A 0 to ±7.07 VDC
EXT GAIN
(External Gain) input signal corresponds to 0 to ±full scale programmed voltage output.
This option selects IEC 725 reference impedance (0.40+j0.25) Ω.
FLICKER
(Source Impedance)
This option should be used for external AC input signals between DC
LOW FREQ
(Low and 40 Hz (the maximum VA rating must be derated). Also, use for IEC
1000-3-2 and IEC 1000-3-3 testing. The RMS servo is bypassed. As a
Frequency)
result, load regulation is a function of output impedance, and RMS
current limit (voltage foldback) is disabled.
Use this option to configure rear panel clock/lock signal as input or
CLOCK/LOCK
output. When configured as input, the power outputs will attempt to
sync to clock/lock input frequency. Target output frequency is
determined by frequency value entered in Program Menu FREQ field.
Target frequency should be entered before clock/lock is configured as
output. Input configuration process is as follows:
1. Enter target frequency in Program Menu FREQ field.
2. Go to System External Menu and enable CLOCK/LOCK option by
3. The unit will now attempt to lock to the input signal; this process
4. Close the output relay.
5. Clock/lock input frequency is continually compared to the target
When configured as an output, clock/lock signal outputs a square wave
of the same frequency as the power outputs. Select OFF to disable.
OFF will configure clock/lock as an input with the PLL mode disabled.
3-26
selecting IN.
can take up to 5 seconds. Phase lock is indicated on the LCD by
the θ symbol to the right of the OUTPUT [ON/OFF] status. Output
relay is not allowed to close until phase lock has been established.
frequency. If input frequency changed more than ±10%, output
relay will open and an error message will be displayed.
Table 3–3 System External Menu
SW 5550AE • SW 3700AE • SW 1850AE
Operation Manual