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Signal
Type
Name
A17
O
Address Line 17. Output to memory as the 18th external address bit
(A17) in extended bus applications, depending on the values of bits
RD0 and RD1 in configuration byte UCONFIG0 (see Chapter 4,
"Device Configuration," of the 8xC251SA, 8xC251SB, 8xC251SP,
8xC251SQ Embedded Microcontroller User's Manual (272795). See
also RD# and PSEN#.
A16
O
Address Line 16. See RD#.
A15:8*
O
Address Lines. Upper address lines for the external bus.
A7:0
I/O
Address/Data Lines. Multiplexed lower address lines and data lines
for external bus.
ALE
O
Address Latch Enable. ALE signals the start of an external bus
cycle and indicates that valid address information is available on lines
A15:8 and A7:0. An external latch can use ALE to demultiplex the
address from the address/data bus.
CEX0
I/O
Programmable Counter Array (PCA) input/output pins. These are
CEX1
input signals for the PCA capture mode and output signals for the
CEX2
PCA compare mode and PCA PWM mode.
CEX3
CEX4
EA#
I
External Access. Direct program accesses to on-chip or off-chip
code memory. For EA# = 0, all program memory accesses are off
chip. For EA# = 1, all program memory accesses are on-chip if the
address is within the range of the on-chip program memory; other-
wise the access is off-chip. The value of EA# is latched at reset. For
devices without on-chip program memory, EA# must be strapped to
ground.
ECI
I
PCA External Clock Input. External clock input to the 16 bit PCA
timer.
INT1:0#
I
External Interrupts 0 and 1. These inputs set IE1:0 in the TCON
register. If bits IT1:0 in the TCON register are set, units IE1:0 are set
by the falling edge on the INT1#/INT0#. If bits IT1:0 are clear, bits
IE1:0 are set by a low level on INTO1:0#.
P0.7:0
I/O
Port 0. This is an 8 bit, open drain, bidirectional I/O port.
P1.0
I/O
Port 1. This is an 8 bit, bidirectional I/O port with internal pullups.
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.7:0
I/O
Port 2. This is an 8 bit, bidirectional I/O port with internal pullups.
* The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for non page mode configuration. If configured in
page mode, Port 0 carries the lower address bits (A7:0) and Port 2 carries the upper address bits (A15:8)
and the data (D7:0)
Table 2. 8xC251Tx Signal Descriptions (Sheet 1 of 3)
8xC251Tx Hardware Description
Description
3
Alternate
Function
P1.7/CEX4/
WCLK
P3.7/RD#
P2.7:0
P0/7:0
P1.3/TXD1
P1.4
P1.5
P1.6/WAIT#
P1.7/A17/
WCLK
P1.2/RXD1
P3.3:2
AD7:0
T2
T2EX
ECI/RXD1
CEX0/TXD1
CEX1
CEX2
CEX3/WAIT#
CEX4/A17/
WCLK
A15:8
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