Table of Contents
Advertisement
Signal
Type
Name
V
PWR
Secondary Supply Voltage 2. This supply voltage connection is pro-
CC2
vided to reduce power supply noise. Connection of this spin to the
+5V supply voltage is recommended. However, when using the ZX3
as a pin for pin replacement for the 8XC51FX, V
nected without loss of compatibility (Not available on DIP).
V
GND
Circuit Ground. Connect this pin to ground.
SS
V
GND
Secondary Ground. This ground is provided to reduce ground
SS1
bounce and improve power supply bypassing. Connection of this pin
to ground is recommended. However, when using the ZX3 as a pin
for pin replacement for the 8XC51FX, V
out loss of compatibility. (Not available in DIP).
V
GND
Secondary Ground 2. This ground is provided to reduce ground
SS2
bounce and improve power supply bypassing. Connection of this pin
to ground is recommended. However, when using the ZX3 as a pin
for pin replacement for the 8XC51FX, V
out loss of compatibility. (Not available in DIP).
WAIT#
I
Real-time Wait State Input. The real-time WAIT# input is enabled by
writing a logical "1" to the WCON.0 (RTWE) bit at S:A7H. During bus
cycles, the external memory system can signal 'system ready' to the
microprocessor in real time by controlling the WAIT# input signal
WCLK
O
Wait Clock Output. The real-time Wait Clock output is driven by writ-
ing a logical "1" to the WCON.1 (RTWCE) bit at S:A7H. When
enabled, the WCLK output produces a square wave signal with a
period of one-half the oscillator frequency
WR#
O
Write. Write signal output to external memory. Asserted for the mem-
ory address range specified by configuration byte UCONFIG0, bits
RD1:0.
XTAL1
I
Input to On-chip, Inverting Oscillator Amplifier. To use the internal
oscillator, a crystal/resonator circuit is connected to this pin. If an
external oscillator is used, its output is connected to this pin. XTAL1 is
the clock source for the internal timing
XTAL2
O
Output of the On-chip, Inverting Oscillator Amplifier. To use the
internal oscillator, a crystal/resonator circuit is connected to this pin. If
an external oscillator is used, leave XTAL2 unconnected.
* The descriptions of A15:8/P2.7:0 and AD7:0/P0.7:0 are for non page mode configuration. If configured in
page mode, Port 0 carries the lower address bits (A7:0) and Port 2 carries the upper address bits (A15:8)
and the data (D7:0)
Table 2. 8xC251Tx Signal Descriptions (Sheet 3 of 3)
8xC251Tx Hardware Description
Description
CC2
can be unconnected with-
SS1
can be unconnected with-
SS1
5
Alternate
Function
can be uncon-
P1.6/CEX3
P1.7/CEX4/
A17
P3.6
Advertisement
Table of Contents
