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PTSSEL
The PTS select (PTSSEL) register selects either a PTS microcode routine or a standard interrupt
service routine for each interrupt request. Setting a bit selects a PTS microcode routine; clearing a bit
selects a standard interrupt service routine. In PTS modes that use the PTSCOUNT register, hardware
clears the corresponding PTSSEL bit when PTSCOUNT reaches zero. The end-of-PTS interrupt service
routine must reset the PTSSEL bit to re-enable the PTS channel.
15
LA
—
7
—
15
LB
—
7
J1850RX
15
LD
—
7
—
Bit
Number
†
14:0
Setting a bit causes the corresponding interrupt to be handled by a PTS microcode routine.
The PTS interrupt vector locations are as follows:
Bit Mnemonic Interrupt
EXTINT
†
Reserved
RI
TI
SSIO1
SSIO0
J1850ST (LB)
J1850RX(LB)
J1850TX(LB)
AD (LA, LB)
EPA0
EPA1
EPA2
EPA3
††
EPA x
††
PTS service is not useful for shared interrupts because the PTS cannot readily
determine the source of these interrupts.
†
Bit 13 is reserved on the 8XC196L x devices and bits 6–8 are reserved on the 87C196LA and
83C196LD. For compatibility with future devices, write zeros to these bits.
EXTINT
—
RI
—
AD
EPA0
EXTINT
—
RI
J1850TX
AD
EPA0
EXTINT
—
RI
—
—
EPA0
EXTINT pin
—
SIO Receive
SIO Transmit
SSIO 1 Transfer
SSIO 0 Transfer
J1850 Status
J1850 Receive
J1850 Transmit
A/D Conversion Complete
EPA Capture/Compare Channel 0
EPA Capture/Compare Channel 1
EPA Capture/Compare Channel 2
EPA Capture/Compare Channel 3
Multiplexed EPA
Figure 4-5. PTS Select (PTSSEL) Register
STANDARD AND PTS INTERRUPTS
Reset State:
TI
SSIO1
EPA1
EPA2
TI
SSIO1
EPA1
EPA2
TI
SSIO1
EPA1
EPA2
Function
PTS Vector
205CH
205AH
2058H
2056H
2054H
2052H
2050H
204EH
204CH
204AH
2048H
2046H
2044H
2042H
2040H
Address:
0004H
0000H
8
SSIO0
—
0
EPA3
EPA x
8
SSIO0
J1850ST
0
EPA3
EPA x
8
SSIO0
—
0
EPA3
EPA x
4-7
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