Intel 87C196CA Supplement To User’s Manual page 5

8.6 PROGRAMMING THE J1850 CONTROLLER ............................................................ 8-16
8.6.1 Programming the J1850 Command (J_CMD) Register ..........................................8-16
8.6.2 Programming the J1850 Configuration (J_CFG) Register ......................................8-18
8.6.3 Programming the J1850 Delay Compensation (J_DLY) Register ...........................8-19
8.6.4 Programming the J1850 Status (J_STAT) Register ................................................8-21
CHAPTER 9
MINIMUM HARDWARE CONSIDERATIONS
9.1 IDENTIFYING THE RESET SOURCE........................................................................... 9-1
9.2 DESIGN CONSIDERATIONS FOR 8XC196LA, LB, AND LD ....................................... 9-2
CHAPTER 10
SPECIAL OPERATING MODES
10.1 INTERNAL TIMING...................................................................................................... 10-1
10.2 ENTERING AND EXITING ONCE MODE ................................................................... 10-2
CHAPTER 11
PROGRAMMING THE NONVOLATILE MEMORY
11.1 SIGNATURE WORD AND PROGRAMMING VOLTAGE VALUES............................. 11-1
11.2 OTPROM ADDRESS MAP .......................................................................................... 11-1
11.3 SLAVE PROGRAMMING CIRCUIT AND ADDRESS MAP ......................................... 11-2
11.4 SERIAL PORT PROGRAMMING CIRCUIT AND ADDRESS MAP............................. 11-4
APPENDIX A
SIGNAL DESCRIPTIONS
A.1 FUNCTIONAL GROUPINGS OF SIGNALS ................................................................. A-1
A.2 DEFAULT CONDITIONS .............................................................................................. A-7
GLOSSARY
CONTENTS
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