Intel 8086 Specification Sheet page 9

can occur between 8086 bus cycles These are re-
ferred to as ''Idle'' states (T
The processor uses these cycles for internal house-
keeping
During T of any bus cycle the ALE (Address Latch
1
Enable) signal is emitted (by either the processor or
the 8288 bus controller depending on the MN MX
strap) At the trailing edge of this pulse a valid ad-
dress and certain status information for the cycle
may be latched
Status bits S S and S
0 1 2
mode by the bus controller to identify the type of
bus transaction according to the following table
) or inactive CLK cycles
i
are used in maximum
Figure 5 Basic System Timing
S S S
2 1 0
0 (LOW) 0 0 Interrupt Acknowledge
0 0 1 Read I O
0 1 0 Write I O
0 1 1 Halt
1 (HIGH) 0 0 Instruction Fetch
1 0 1 Read Data from Memory
1 1 0 Write Data to Memory
1 1 1 Passive (no bus cycle)
8086
Characteristics
231455 – 8
9