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Symbol
Pin No
QS
QS
24 25
1
0
The following pin function descriptions are for the 8086 in minimum mode (i e MN MX
functions which are unique to minimum mode are described all other pin functions are as described above
M IO
28
O
WR
29
O
INTA
24
O
ALE
25
O
DT R
27
O
DEN
26
O
HOLD
31 30
I O
HLDA
Table 1 Pin Description (Continued)
Type
O
QUEUE STATUS The queue status is valid during the CLK cycle after
which the queue operation is performed
QS
and QS
provide status to allow external tracking of the internal
1
0
8086 instruction queue
QS
1
0 (LOW)
0
1 (HIGH)
1
STATUS LINE logically equivalent to S
distinguish a memory access from an I O access M IO becomes valid in
the T
preceding a bus cycle and remains valid until the final T
4
(M
HIGH IO
LOW) M IO floats to 3-state OFF in local bus ''hold
e
e
acknowledge''
WRITE indicates that the processor is performing a write memory or write
I O cycle depending on the state of the M IO signal WR is active for T
and T
of any write cycle It is active LOW and floats to 3-state OFF in
W
local bus ''hold acknowledge''
INTA is used as a read strobe for interrupt acknowledge cycles It is active
LOW during T
T
and T
2
3
ADDRESS LATCH ENABLE provided by the processor to latch the
address into the 8282 8283 address latch It is a HIGH pulse active during
T
of any bus cycle Note that ALE is never floated
1
DATA TRANSMIT RECEIVE needed in minimum system that desires to
use an 8286 8287 data bus transceiver It is used to control the direction of
data flow through the transceiver Logically DT R is equivalent to S
maximum mode and its timing is the same as for M IO (T
LOW ) This signal floats to 3-state OFF in local bus ''hold acknowledge''
DATA ENABLE provided as an output enable for the 8286 8287 in a
minimum system which uses the transceiver DEN is active LOW during
each memory and I O access and for INTA cycles For a read or INTA cycle
it is active from the middle of T
it is active from the beginning of T
state OFF in local bus ''hold acknowledge''
HOLD indicates that another master is requesting a local bus ''hold '' To be
acknowledged HOLD must be active HIGH The processor receiving the
''hold'' request will issue HLDA (HIGH) as an acknowledgement in the
middle of a T
or T
clock cycle Simultaneous with the issuance of HLDA
4
i
the processor will float the local bus and control lines After HOLD is
detected as being LOW the processor will LOWer the HLDA and when the
processor needs to run another cycle it will again drive the local bus and
control lines Hold acknowledge (HLDA) and HOLD have internal pull-up
resistors
The same rules as for RQ GT apply regarding when the local bus will be
released
HOLD is not an asynchronous input External synchronization should be
provided if the system cannot otherwise guarantee the setup time
Name and Function
QS
Characteristics
0
0
No Operation
1
First Byte of Op Code from Queue
0
Empty the Queue
1
Subsequent Byte from Queue
in the maximum mode It is used to
2
of each interrupt acknowledge cycle
W
until the middle of T
2
4
until the middle of T
2
8086
V
) Only the pin
e
CC
of the cycle
4
T
2
3
in the
1
HIGH R
e
e
while for a write cycle
DEN floats to 3-
4
5
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