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8086
The following pin function descriptions are for 8086 systems in either minimum or maximum mode The ''Local
Bus'' in these descriptions is the direct multiplexed bus interface connection to the 8086 (without regard to
additional bus buffers)
Symbol
Pin No
AD
–AD
2 – 16 39
15
0
A
S
35 – 38
19
6
A
S
18
5
A
S
17
4
A
S
16
3
BHE S
34
7
RD
32
2
Table 1 Pin Description
Type
I O
ADDRESS DATA BUS These lines constitute the time multiplexed
memory IO address (T
analogous to BHE for the lower byte of the data bus pins D
LOW during T
when a byte is to be transferred on the lower portion
1
of the bus in memory or I O operations Eight-bit oriented devices tied
to the lower half would normally use A
functions (See BHE ) These lines are active HIGH and float to 3-state
OFF during interrupt acknowledge and local bus ''hold acknowledge''
O
ADDRESS STATUS During T
address lines for memory operations During I O operations these
lines are LOW During memory and I O operations status information
is available on these lines during T
interrupt enable FLAG bit (S
CLK cycle A
S
17
4
This information indicates which relocation register is presently being
used for data accessing
These lines float to 3-state OFF during local bus ''hold acknowledge ''
A
S
17
4
0 (LOW)
0
1 (HIGH)
1
S
is 0
6
(LOW)
O
BUS HIGH ENABLE STATUS During T
(BHE) should be used to enable data onto the most significant half of
the data bus pins D
half of the bus would normally use BHE to condition chip select
functions BHE is LOW during T
acknowledge cycles when a byte is to be transferred on the high
portion of the bus The S
T
and T
The signal is active LOW and floats to 3-state OFF in
3
4
''hold'' It is LOW during T
BHE
0
0
1
1
O
READ Read strobe indicates that the processor is performing a
memory or I O read cycle depending on the state of the S
signal is used to read devices which reside on the 8086 local bus RD
is active LOW during T
guaranteed to remain HIGH in T
This signal floats to 3-state OFF in ''hold acknowledge''
Name and Function
) and data (T
T
T
1
2
3
W
to condition chip select
0
these are the four most significant
1
T
T
T
2
3
W
4
) is updated at the beginning of each
5
and A
S
are encoded as shown
16
3
A
S
Characteristics
16
3
0
Alternate Data
1
Stack
0
Code or None
1
Data
the bus high enable signal
1
– D
Eight-bit oriented devices tied to the upper
15
8
for read write and interrupt
1
status information is available during T
7
for the first interrupt acknowledge cycle
1
A
Characteristics
0
0
Whole word
1
Upper byte from to odd address
0
Lower byte from to even address
1
None
T
and T
of any read cycle and is
2
3
W
until the 8086 local bus has floated
2
T
) bus A
is
4
0
–D
It is
7
0
The status of the
2
pin This
2
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