Intel 8086 Specification Sheet page 18

8086
WAVEFORMS
(Continued)
MINIMUM MODE (Continued)
SOFTWARE HALT
RD WR INTA V
e
OH
DT R INDETERMINATE
e
NOTES
1 All signals switch between V
2 RDY is sampled near the end of T
3 Two INTA cycles run back-to-back The 8086 LOCAL ADDR DATA BUS is floating during both INTA cycles Control
signals shown for second INTA cycle
4 Signals at 8284A are shown for reference only
5 All timing measurements are made at 1 5V unless otherwise noted
18
and V unless otherwise specified
OH OL
T T to determine if T
2 3 W
machines states are to be inserted
W
231455 –14