Intel 8086 Specification Sheet page 3

Symbol Pin No Type
READY 22
INTR 18
TEST 23
NMI 17
RESET 21
CLK 19
V 40
CC
GND 1 20
MN MX 33
The following pin function descriptions are for the 8086 8288 system in maximum mode (i e MN MX
Only the pin functions which are unique to maximum mode are described all other pin functions are as
described above
S S S 26– 28 O
2 1 0
Table 1 Pin Description (Continued)
I READY is the acknowledgement from the addressed memory or I O
device that it will complete the data transfer The READY signal from
memory IO is synchronized by the 8284A Clock Generator to form
READY This signal is active HIGH The 8086 READY input is not
synchronized Correct operation is not guaranteed if the setup and hold
times are not met
I INTERRUPT REQUEST is a level triggered input which is sampled
during the last clock cycle of each instruction to determine if the
processor should enter into an interrupt acknowledge operation A
subroutine is vectored to via an interrupt vector lookup table located in
system memory It can be internally masked by software resetting the
interrupt enable bit INTR is internally synchronized This signal is
active HIGH
I TEST input is examined by the ''Wait'' instruction If the TEST input is
LOW execution continues otherwise the processor waits in an ''Idle''
state This input is synchronized internally during each clock cycle on
the leading edge of CLK
I NON-MASKABLE INTERRUPT an edge triggered input which causes
a type 2 interrupt A subroutine is vectored to via an interrupt vector
lookup table located in system memory NMI is not maskable internally
by software A transition from LOW to HIGH initiates the interrupt at the
end of the current instruction This input is internally synchronized
I RESET causes the processor to immediately terminate its present
activity The signal must be active HIGH for at least four clock cycles It
restarts execution as described in the Instruction Set description when
RESET returns LOW RESET is internally synchronized
I CLOCK provides the basic timing for the processor and bus controller
It is asymmetric with a 33% duty cycle to provide optimized internal
timing
V 5V power supply pin
a
CC
GROUND
I MINIMUM MAXIMUM indicates what mode the processor is to
operate in The two modes are discussed in the following sections
STATUS active during T
(1 1 1) during T or during T
3
by the 8288 Bus Controller to generate all memory and I O access control
signals Any change by S
beginning of a bus cycle and the return to the passive state in T
used to indicate the end of a bus cycle
Name and Function
T and T and is returned to the passive state
4 1 2
when READY is HIGH This status is used
W
S or S during T is used to indicate the
2 1 0 4
8086
V )
e
SS
or T is
3 W
3