Table of Contents
Advertisement
5.5.2 The ROM Bus
The CPU communicates with the internal ROM by means of the ROM bus. The bus is divided into
three parts: the physical address bus, the data bus, and the control signals. The ROM bus connects the
CPU to the plug-in ROM assembly by means of the ROM receptacle. Refer to table 10-2 for the ROM
receptacle pin assignments.
TIt.
ROM Ph,.1U1
Add,. ...... (A1 Tltrougla A17J.
The 17-bit unidirectional physical address bus is
driven by the CPU. The 17 physical address bits correspond directly to logical address bits Al through
A17 in the CPU. AO is a bit that distinguishes the upper byte from the lower byte in a 16-bit word. It
is internal to the CPU and does not appear on the address bus .
...... ROil DatIIlu. (DO Through
D15J.
The 16-bit bidirectional three-state data bus provides the gen-
eral-purpose data path for the system. It can accept data in either word (16-bit) or byte (8-bit) length.
The upper byte of the data bus includes 08 through 015; the lower byte includes DO through 07. The
upper and lower bytes of a word
are
always enabled during an internal ROM access .
...... ROM Control 51_I •• The ROM control signals include four ROM-select signals and RDTACK.
The ROM-select signals are decoded by IC U19 on the logic A peA. Each of these signals (ROMO,
ROMI, ROM2, and ROM3) selects a 256K-byte block of ROM address space in the plug-in ROM
assembly. Table 5-4 shows the address range enabled by each ROM-select Signal.
Tala •• 5-4. ROII·SeI.ct Addre •• _
. . .
RO .. • ..... Slg ....
Addr ..........
ROMO
0OOOOO-03FFFF
ROMI
040000-07FFFF
ROM2
080000-0BFFFF
ROM3
OCOOOO-OFFFFF
ROTACK is
the ROM data transfer acknowledge signal.
This
signal (by going low) indicates that the
data transfer portion of a bus cycle is completed. When the mainframe recognizes RDTACK during a
read cycle, data is latched and the bus cycle is terminated.
5.8 MMU
The MMU (Memory-Management Unit) consists of a 4 by 12-bit register file (ICs U55 through US7)
and a 12-bit full adder (ICs U47 through U49), all mounted on the logic A PCA. Its function is to
perform address mapping.
5.6.1
Address Mapping
Mapping is performed during RAM operations only; that is, when the most significant bit of the phys-
ical address (PAl3) is high.
During a RAM access, the contents of one of the registers in the register file is added to logical address
bits All through A22 of the CPU, forming the physical address. Since logical address bits Al through
AIO are unmapped, the minimum segment size
is 2K-bytes (IK-words). The adder is enabled only
during a RAM access; therefore, mapping can be performed only within the RAM address space.
Advertisement
Table of Contents
