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1.3
Interface Descriptions
1.3.1
The PCI Interface
1.3.2
The SCSI Interface
This section provides a more detailed explanation about the PCI
Interface, the SCSI Interface, and Ultra SCSI.
PCI is a high-speed standard local bus for interfacing a number of I/O
components to the processor and memory subsystems in a high end PC.
The PCI functionality for the LSIU40SE is contained within the
LSI53C876 PCI to Ultra SCSI I/O Processor chip. The LSI53C876
connects directly to the PCI bus and generates timing protocol in
compliance with the PCI Local Bus Specification Revision 2.1 standard.
The PCI interface operates as a 32-bit DMA bus master. The connection
is made through edge connector J1 (see
definitions and pin numbers conform to the PCI Local Bus Specification
Revision 2.1 standard. The LSIU40SE conforms to the PCI universal
signaling environment for a 5 V or 3.3 V PCI bus.
The SCSI functionality for the LSIU40SE is contained within the
LSI53C876. The LSI53C876 connects directly to the two SCSI buses and
generates timing and protocol in compliance with the SCSI standard.
The SCSI interfaces on the LSIU40SE operate as 16-bit, synchronous or
asynchronous, SE bus, and support Ultra SCSI protocols and 16-bit
arbitration. Each interface is made through two of the connectors J2, J3,
and J4 (for Channel A), or J6, J7, and J8 (for Channel B). Connectors
J2 and J6 are 68-pin high density right-angle receptacles. Connectors J3
and J7 are shielded 68-pin VHDCI 0.8 mm right-angle receptacles that
protrude through the back panel bracket. Connectors J4 and J8 are
50-pin low density vertical shrouded pin headers. See
location of these connectors.
SE SCSI active termination is provided on the LSIU40SE. Termination is
automatically enabled when only one of the connectors J2, J3, and, J4
(or J6, J7, and, J8) is used, or when an 8-bit device is connected to the
16-bit J3 or J7 connectors. In the latter case, only the upper 8 data bits
are automatically terminated. The LSIU40SE supplies SCSI bus
Interface Descriptions
Figure
2.1). The signal
Figure 2.1
for the
1-3
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