Table 2.9:Counter/Timer Control Register Bit Map - Advantech UNO-2050G User Manual

Counter/Timer Control Register
The Counter/Timer Control Register controls the function and status of
each counter/timer signal source. Table 2-9 shows the bit map of the
Counter/Timer Control Register. The register is readable/writable regis-
ter. While being written, it is used as a control register; and while being
read, it is used as a status register
Table 2.9: Counter/Timer Control Register Bit Map
Base Address
Base+07H R/W Interrupt Flag/Clear Register
Base+08H R/W 82C54 Chip Counter0 Register
Base+09H R/W 82C54 Chip Counter1 Register
Base+0BH R/W 82C54 Chip Control Register
Base+0CH R/W Counter0 Start Control / Output Status Register
Base+0DH R/W Counter1 Start Control / Output Status Register
Base+0EH R/W Counter0 Setting Register
Base+0FH R/W Counter1 Setting Register
CTR0F & CTR1F: Counter 0 & Counter 1 interrupt flag bit
CTR0Gate & CTR1Gate: Counter 0 and Counter 1 gate control bit
CTR0Out & CTR1Out: Counter 0 and Counter 1 output status bit
CTR0CLKSet & CTR1CLKSet: Counter 0 and 1 clock source control bit
CTR0GateSet & CTR1GateSet: Counter 0 and 1 gate source control bit
CTR0OutSet & CTR1OutSet: Counter 0 & 1 output destination controlbit
CTR0IntSet & CTR1IntSet: Counter 0 and Counter 1 interrupt control bit
S0 & S1: Counter 0 and 1 internal clock control bit
CTR32Set: Cascaded 32-bit counter control bit
UNO-2050G User Manual
7 6 5 4
CTR0
Out
CTR1
Out
CTR32 S1 S0
Set
3 2
CTR1F CTR0F
CTR0 CTR0
IntSet OutSet
CTR1 CTR1
IntSet OutSig
16
1 0
CTR0
Gate
CTR1
Gate
CTR0 CTR0
GateSet CLKSet
CTR1 CTR1
GateSig CLKSig