Counter/Timer Control Register - Advantech UNO-3072 User Manual

2.7.1 Counter/Timer Control Register

The Counter/Timer Control Register controls the function and status of
each counter/timer signal source. Table 2.11 shows the bit map of the
Counter/Timer Control Register. The register is readable/writable register.
While being written, it is used as a control register; and while being read,
it is used as a status register.
Table 2.11: Counter/Timer Control Register Bit Map
Base 7
Address
207H R/W Interrupt Flag/Clear Register
208H R/W 82C54 Chip Counter0 Register
209H R/W 82C54 Chip Counter1 Register
20BH R/W 82C54 Chip Control Register
20CH R/W Counter0 Start Control / Output Status Register
20DH R/W Counter1 Start Control / Output Status Register
20EH R/W Counter0 Setting Register
20FH R/W Counter1 Setting Register
CTR0F/CTR1F: (Counter 0/1) interrupt flag bit
CTR0Gate/CTR1Gate: (Counter 0/1) gate control bit
CTR0Out /CTR1Out: (Counter 0/1) output status bit
CTR0CLKSet /CTR1CLKSet: (Counter 0/1) clock source control bit
CTR0GateSet/CTR1GateSet: (Counter 0/1) gate source control bit
CTR0OutSet/CTR1OutSet: (Counter 0 /1) output destination control bit
CTR0IntSet/CTR1IntSet: (Counter 0/1) interrupt control bit
S0/S1: (Counter 0/1) internal clock control bit
CTR32Set: Cascaded 32-bit counter control bit
6 5 4
CTR0
Out
CTR1
Out
CTR32 S1 S0
Set
3 2
CTR1F CTR0F
CTR0 CTR0
IntSet OutSet
CTR1 CTR1
IntSet OutSet
25
1 0
CTR0
Gate
CTR1
Gate
CTR0 CTR0
GateSet CLKSet
CTR1 CTR1
GateSet CLKSet
Chapter 2