Cache Configuration - DFI 486-OCV Plus User Manual

Cache Configuration

The 486-OCV Plus system board can be configured to
three different cache sizes: 64KB, 128KB and 256KB.
128KB of cache memory is the default size. Either
8K x 8 (20ns) or 32K x 8 (20ns) chips are used for
cache depending on the size of cache desired. Regard-
less of the amount of cache memory installed, one 8K x
8 (20ns), one 16K x 8 or one 32K x 8 (20ns) SRAM is
needed for tag RAM to store the cacheable addresses.
Because only one SRAM is installed for tag RAM, the
cacheable system RAM size is dependent on the size of
cache installed on your system board. The system board
can automatically detect the cacheable system RAM size
based on the size of cache installed in the 486-OCV Plus
system board.
The following table summarizes the cacheable system
RAM size for the corresponding cache size.
Cache Memory
64KB
128KB
256KB
Important:
When cache size is 64KB or 128KB, an 8K x 8 (20ns)
SRAM should be inserted in socket U3 for tag RAM.
When cache size is 256KB, use a 16K x 8 or 32K x 8
(20ns) SRAM.
Cacheable System RAM Size
16MB and below
32MB and below
64MB (maximum memory)
Installation Overview u 2-14
486-OCV Plus