DFI 486-OCV Plus User Manual page 59

RAM Module
The DRAM memory on the 486-OCV Plus system board
can be expanded to a total of 64MB using 256Kx36,
512Kx36, 1Mx36, 2Mx36, 4Mx36 and 8Mx36
HSIMMs. The DRAM controller uses a page mode
design with an access time of 80ns or less.
Cache Module
The 486-OCV Plus supports 64KB/128KB of direct map
cache using 8Kx8 (20ns) SRAMs or 256KB using
32Kx8 (20ns) SRAMs.
Burst Cycles
The 486 microprocessor accepts burst cycles for any bus
request that requires more than one data cycle. During
burst cycles, a new data item is strobed into the 486
microprocessor for every clock, rather than every other
clock as in non-burst cycles.
486-OCV Plus
Appendix F u F-4