Intel SL3QA - Pentium III 550 MHz Processor Specification page 52

restarting the instruction may cause unexpected system behavior due to the
repetition of the side-effect.
Workaround: Code which performs loads from memory that has side-effects can effectively
workaround this behavior by using simple integer-based load instructions when
accessing side-effect memory and by ensuring that all code is written such that a
code segment limit violation cannot occur as a part of reading from side-effect
memory.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E23. Read Portion of RMW Instruction May Execute Twice
Problem: When the Pentium III processor executes a read-modify-write (RMW) arithmetic
instruction, with memory as the destination, it is possible for a page fault to occur
during the execution of the store on the memory operand after the read operation
has completed but before the write operation completes.
If the memory targeted for the instruction is UC (uncached), memory will observe the
occurrence of the initial load before the page fault handler and again if the instruction
is restarted.
Implication: This erratum has no effect if the memory targeted for the RMW instruction has no
side-effects. If, however, the load targets a memory region that has side-effects,
multiple occurrences of the initial load may lead to unpredictable system behavior.
Workaround: Hardware and software developers who write device drivers for custom hardware
that may have a side-effect style of design should use simple loads and simple stores
to transfer data to and from the device. Then, the memory location will simply be
read twice with no additional implications.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E24. MC2_STATUS MSR Has Model-Specific Error Code and Machine Check
Architecture Error Code Reversed
Problem: The Intel Architecture Software Developer's Manual, Volume 3: System Programming
Guide, documents that for the MCi_STATUS MSR, bits 15:0 contain the MCA
(machine-check architecture) error code field, and bits 31:16 contain the model-
specific error code field. However, for the MC2_STATUS MSR, these bits have been
reversed. For the MC2_STATUS MSR, bits 15:0 contain the model-specific error code
field and bits 31:16 contain the MCA error code field.
Implication: A machine check error may be decoded incorrectly if this erratum on the
MC2_STATUS MSR is not taken into account.
Workaround: When decoding the MC2_STATUS MSR, reverse the two error fields.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E25. Mixed Cacheability of Lock Variables Is Problematic in MP Systems
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Errata
Specification Update