Intel SL3QA - Pentium III 550 MHz Processor Specification page 48

Problem: The Memory Type field for nonmemory transactions such as I/O and Special Cycles
are undefined. Although the Memory Type attribute for nonmemory operations
logically should (and usually does) manifest itself as UC, this feature is not designed
into the implementation and is therefore inconsistent.
Implication: Bus agents may decode a non-UC memory type for nonmemory bus transactions.
Workaround: Bus agents must consider transaction type to determine the validity of the
Memory Type field for a transaction.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E19. Infinite Snoop Stall During L2 Initialization of MP Systems
Problem: It is possible for snoop traffic generated on the system bus while a processor is
executing its L2 cache initialization routine to cause the initializing processor to hang.
Implication: A DP (2-way) system which does not suppress snoop traffic while L2 caches are being
initialized may hang during this initialization sequence.
The system BIOS can create an execution environment which allows processors to
initialize their L2 caches without the system generating any snoop traffic on the bus.
Below is a pseudo-code fragment, designed explicitly for a two-processor system,
that uses a serial algorithm to initialize each processor's L2 cache:
48
Suppress_all_I/O_traffic()
K = 0;
while (K <= 1)
{
/* Obtain current value of K. This forces both Temp and K into */
/* the L1 cache. Note that Temp could also be maintained in a */
/* general purpose register. */
Temp = K;
Wait_until_all_processors_are_signed_in_at_barrier()
if ( logical_proc_APIC_id == K ) {
{
wait_10_usecs_delay_loop(); /* this time delay, required */
/* in the worst case, allows */
/* the barrier semaphore to */
Errata
Specification Update