Intel SL3QA - Pentium III 550 MHz Processor Specification page 41

Errata
After losing the BSP arbitration, the AP goes into a wait loop, waiting for a
STARTUP_IPI.
The BSP can wake up the AP to perform some tasks with a STARTUP_IPI, and then
put it back to sleep with an initialization inter-processor interrupt (INIT_IPI, which
has the same effect as asserting INIT#), which returns it to a wait loop. The result is
a possible loss of cache coherency if the off-line processor is intended to service a
FLUSH# assertion at this point. The FLUSH# will be serviced as soon as the processor
is awakened by a STARTUP_IPI, before any other instructions are executed. Intel has
not encountered any operating systems that are affected by this erratum.
Workaround: Operating system developers should take care to execute a WBINVD instruction
before the AP is taken off-line using an INIT_IPI
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E4. Code Fetch Matching Disabled Debug Register May Cause Debug
Exception
Problem: The bits L0 3 and G0 3 enable breakpoints local to a task and global to all tasks,
respectively. If one of these bits is set, a breakpoint is enabled, corresponding to the
addresses in the debug registers DR0-DR3. If at least one of these breakpoints is
enabled, any of these registers are disabled (i.e., Ln and Gn are 0), and RWn for the
disabled register is 00 (indicating a breakpoint on instruction execution), normally an
instruction fetch will not cause an instruction-breakpoint fault based on a match with
the address in the disabled register(s). However, if the address in a disabled register
matches the address of a code fetch which also results in a page fault, an instruction-
breakpoint fault will occur.
Implication: The bits L0 3 and G0 3 enable breakpoints local to a task and global to all tasks,
respectively. If one of these bits is set, a breakpoint is enabled, corresponding to the
addresses in the debug registers DR0-DR3. If at least one of these breakpoints is
enabled, any of these registers are disabled (i.e., Ln and Gn are 0), and RWn for the
disabled register is 00 (indicating a breakpoint on instruction execution), normally an
instruction fetch will not cause an instruction-breakpoint fault based on a match with
the address in the disabled register(s). However, if the address in a disabled register
matches the address of a code fetch which also results in a page fault, an instruction-
breakpoint fault will occur.
Implication: While
encountered if breakpoint registers are not cleared when they are disabled. Debug
software which does not implement a code breakpoint handler will fail, if this occurs.
If a handler is present, the fault will be serviced. Mixing data and code may
exacerbate this problem by allowing disabled data breakpoint registers to break on
an instruction fetch.
Workaround: The debug handler should clear breakpoint registers before they become disabled
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E5. Double ECC Error on Read May Result in BINIT#
Specification Update
debugging software, extraneous instruction-breakpoint faults may be
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