Intel SL3QA - Pentium III 550 MHz Processor Specification page 59

Errata
The P6 architecture allows for instructions (1) and (7) in P0 to be dispatched to the
L1 cache simultaneously. If the two instructions are accessing the same memory
bank in the L1 cache, the load (7) will be given higher priority and will complete,
blocking instruction (1).
Instructions (8) and (9) may then execute and retire, placing the instruction pointer
back to instruction (7). This is due to the condition at the end of the "wait0" loop
being false. The livelock scenario can occur if the timing of the wait0 loop execution is
such that instruction (7) in P0 is ready for completion every time that instruction (1)
tries to complete. Instruction (7) will again have higher priority, preventing the data
([xyz]) in instruction (1) from being written to the L1 cache. This causes instruction
(6) in P0 to not complete and the sequence "wait0" to loop infinitely in P0.
A livelock condition also occurs in P1 because instruction (6) in P0 does not complete
(blocked by instruction (1) not completing). The problem with this scenario is that P0
should eventually allow for instruction (1) to write its data to the L1 cache. If this
occurs, the data in instruction (6) will be written to memory, allowing the conditions
in both loops to be true.
Implication: Both processors will be stuck in an infinite loop, leading to a hang condition. Note
that if P0 receives any interrupt, the loop timing will be disrupted such that the
livelock will be broken. The system timer, a keystroke, or mouse movement can
provide an interrupt that will break the livelock.
Workaround: Use a LOCK instruction to force P0 to execute instruction (6) before instruction
(7).
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E40. System Bus Address Parity Generator May Report False AERR#
Problem: The processor's address parity error detection circuit may fail to meet its frequency
timing specification under certain environmental conditions. At the high end of the
temperature specification and/or the low end of the voltage range, the processor may
report false address parity errors.
Implication: If the system has AERR# drive enabled (bit [3] of the EBL_CR_POWERON resister set
to '1') spurious address detection and reporting may occur. In some system
configurations, BINIT# may be asserted on the system bus. This may cause some
systems to generate a machine check exception and in others may cause a reboot.
Workaround: Disable AERR# drive from the processor. AERR# drive may be disabled by
clearing bit [3] in the EBL_CR_POWERON register. In addition, if the chipset allows,
AERR# drive should be enabled from the chipset and AERR# observation enabled on
the processor. AERR# observation on the processor is enabled by asserting A8# on
the active-to-inactive transition of RESET#.
Status: For the processor part numbers affected see the "Pentium® III Processor
Identification and Packaging Information" table in the General Information section.
E41. System Bus ECC Not Functional With 2:1 Ratio
Specification Update 59