Intel SL3QA - Pentium III 550 MHz Processor Specification page 42

Problem: For this erratum to occur, the following conditions must be met:
• Machine Check Exceptions (MCEs) must be enabled.
• A dataless transaction (such as a write invalidate) must be occurring
simultaneously with a transaction which returns data (a normal read).
• The read data must contain a double-bit uncorrectable ECC error.
If these conditions are met, the Pentium III processor will not be able to determine
which transaction was erroneous, and instead of generating an MCE, it will generate
a BINIT#.
Implication: The bus will be reinitialized in this case. However, since a double-bit uncorrectable
ECC error occurred on the read, the MCE handler (which is normally reached on a
double-bit uncorrectable ECC error for a read) would most likely cause the same
BINIT# event.
Workaround: Though the ability to drive BINIT# can be disabled in the Pentium III processor,
which would prevent the effects of this erratum, overall system behavior would not
improve, since the error which would normally cause a BINIT# would instead cause
the machine to shut down. No other workaround has been identified.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section
E6. FP Inexact-Result Exception Flag May Not Be Set
Problem: When the result of a floating-point operation is not exactly representable in the
destination format (1/3 in binary form, for example), an inexact-result (precision)
exception occurs. When this occurs, the PE bit (bit 5 of the FPU status word) is
normally set by the processor. Under certain rare conditions, this bit may not be set
when this rounding occurs. However, other actions taken by the processor (invoking
the software exception handler if the exception is unmasked) are not affected. This
erratum can only occur if the floating-point operation which causes the precision
exception is immediately followed by one of the following instructions:
• FST m32real
• FST m64real
• FSTP m32real
• FSTP m64real
• FSTP m80real
• FIST m16int
• FIST m32int
• FISTP m16int
• FISTP m32int
• FISTP m64int
42
Errata
Specification Update