Intel SL3QA - Pentium III 550 MHz Processor Specification page 79

Errata
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E84. REP MOVS Operation in Fast String Mode Continues in That Mode
When Crossing into a Page with a Different Memory Type
Problem: A fast "REP MOVS" operation will continue to be handled in fast mode when the string
operation crosses a page boundary into an Uncacheable (UC) memory type. Also if
the fast string operation crosses a page boundary into a WC memory region, the
processor will not self snoop the WC memory region. This may eventually result in
incorrect data for the WC portion of the operation if those cache lines were previously
cached as WB (through aliasing) and modified.
Implication: String elements should be handled by the processor at the native operand size in UC
memory. In the event that the WB to WC aliasing case occurs and incorrect data is
written to memory, the end result would vary from benign to operating system or
application failure. Intel has not observed either aspects of this erratum in
commercially available software.
Workaround: Software operating within Intel's recommendation will not require WB and WC
memory aliased to the same physical address.
Status: For the steppings affected, see the Summary Table of Changes.
E85. The FXSAVE, STOS or MOVS Instructions May Cause a Store Ordering
Violation When Data Crosses a Page with a UC Memory Type
Problem: If the data from an FXSAVE, STOS or MOVS instruction crosses a page boundary from
WB to UC memory type and this instruction is immediately followed by a second
instruction that also issues a store to memory, the final data stores from both
instructions may occur in the wrong order
Implication: The impact of this store ordering behavior may vary from normal software execution
to potential software failure. Intel has not observed this erratum in commercially
available software.
Workaround: FXSAVE, STOS or MOVS data must not cross page boundary from WB to UC
memory type.
Status: For the steppings affected, see the Summary Table of Changes.
E86. POPF and POPFD Instructions that Set the Trap Flag Bit May Cause
Unpredictable Processor Behavior
Problem: In some rare cases, POPF and POPFD instructions that set the Trap Flag (TF) bit in
the EFLAGS register (causing the processor to enter Single-Step mode) may cause
unpredictable processor behavior.
Implication: Single step operation is typically enabled during software debug activities, not during
normal system operation
Specification Update 79