Intel SL3QA - Pentium III 550 MHz Processor Specification page 80

Workaround: There is no workaround for single step operation in commercially available
software. For debug activities on custom software, the POPF and POPFD instructions
could be immediately followed by a NOP instruction to facilitate correct execution.
Status: For the steppings affected, see the Summary Table of Changes.
E87. Code Segment Limit Violation May Occur on 4 Gigabyte Limit Check
Problem: Code Segment limit violation may occur on 4 Gigabyte limit check when the code
stream wraps around in a way that one instruction ends at the last byte of the
segment and the next instruction begins at 0x0.
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: Avoid code that wraps around segment limit.
Status: For the steppings affected, see the Summary Table of Changes.
E88. FST Instruction with Numeric and Null Segment Exceptions May
Cause General Protection Faults to be Missed and FP Linear Address
(FLA) Mismatch
Problem: FST instruction combined with numeric and null segment exceptions may cause
General Protection Faults to be missed and FP Linear Address (FLA) mismatch.
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
E89. Code Segment (CS) is incorrect on SMM Handler when SMBASE is not
Aligned
Problem: With SMBASE being relocated to a non-aligned address, during SMM entry the CS can
be improperly updated which can lead to an incorrect SMM handler.
Implication: This is a rare condition that may result in a system hang. Intel has not observed this
erratum with any commercially available software, or system.
Workaround: Align SMBASE to 32K byte.
Status: For the steppings affected, see the Summary Table of Changes.
E90. Page with PAT (Page Attribute Table) Set to USWC (Uncacheable
Speculative Write Combine) While Associated MTRR (Memory Type
Range Register) is UC (Uncacheable) May Consolidate to UC
Problem: A page whose PAT memory type is USWC while the relevant MTRR memory type is
UC, the consolidated memory type may be treated as UC (rather than WC as
specified in IA-32 Intel® Architecture Software Developer's Manual).
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Errata
Specification Update