Intel SL3QA - Pentium III 550 MHz Processor Specification page 51

Errata
Implication: The effect of incorrect execution will vary from unnoticeable, due to the code
sequence discarding the incorrect bits, to an application failure. If the MMX
technology-enabled application in which MOVD is used to manipulate pixels, it is
possible for one or more pixels to exhibit the wrong color or position momentarily. It
is also possible for a computational application that uses the MOVD instruction in the
manner described above to produce incorrect data. Note that this data may cause an
unexpected page fault or general protection fault
Workaround: There are two possible workarounds for this erratum:
1. Rather than using the MOVSX-MOVD, IMUL-MOVD, or CBW-MOVD pairing to
handle one variable at a time, use the sign extension capabilities (PSRAW, etc.)
within MMX technology for operating on multiple variables. This would result in
higher performance as well.
2. Insert another operation that modifies or copies the sign-extended value between
the MOVSX/IMUL/CBW instruction and the MOVD instruction as in the example
below:
XOR EAX, EAX (or SUB EAX, EAX)
MOVSX AX, BL (or other MOVSX, other IMUL or CBW instruction)
*MOV EAX, EAX
MOVD MM0, EAX
*Note: MOV EAX, EAX is used here as it is fairly generic. Again, EAX can be any 32-
bit register.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E22. Premature Execution of a Load Operation Prior to Exception Handler
Invocation
Problem: This erratum can occur with any of the following situations:
1. If an instruction that performs a memory load causes a code segment limit
violation,
2. If a waiting floating-point instruction or MMX™ instruction that performs a
memory load has a floating-point exception pending, or
3. If an MMX instruction that performs a memory load and has either CR0.EM =1
(Emulation bit set), or a floating-point Top-of-Stack (FP TOS) not equal to 0, or a
DNA exception pending.
If any of the above circumstances occur it is possible that the load portion of the
instruction will have executed before the exception handler is entered.
Implication: In normal code execution where the target of the load operation is to write back
memory there is no impact from the load being prematurely executed, nor from the
restart and subsequent re-execution of that instruction by the exception handler. If
the target of the load is to uncached memory that has a system side-effect,
Specification Update 51