Intel SL3QA - Pentium III 550 MHz Processor Specification page 47

Errata
the store. Examples of page permission tightening include from Present to Not
Present or from Read/Write to Read Only, etc.
3. Another processor, without corresponding synchronization and TLB flush, must
cause the permission change.
Implication: This scenario may only occur on a multiprocessor platform running an operating
system that performs "lazy" TLB shootdowns. The memory image of the EFLAGS
register on the page fault handler's stack prematurely contains the final arithmetic
flag values although the instruction has not yet completed. Intel has not identified
any operating systems that inspect the arithmetic portion of the EFLAGS register
during a page fault nor observed this erratum in laboratory testing of software
applications.
Workaround: No workaround is needed upon normal restart of the instruction, since this
erratum is transparent to the faulting code and results in correct instruction behavior.
Operating systems may ensure that no processor is currently accessing a page that is
scheduled to have its page permissions tightened or have a page fault handler that
ignores any incorrect state.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E17. Near CALL to ESP Creates Unexpected EIP Address
Problem: As documented, the CALL instruction saves procedure linking information in the
procedure stack and jumps to the called procedure specified with the destination
(target) operand. The target operand specifies the address of the first instruction in
the called procedure. This operand can be an immediate value, a general-purpose
register, or a memory location. When accessing an absolute address indirectly using
the stack pointer (ESP) as a base register, the base value used is the value in the
ESP register before the instruction executes. However, when accessing an absolute
address directly using ESP as the base register, the base value used is the value of
ESP after the return value is pushed on the stack, not the value in the ESP register
before the instruction executed.
Implication: Due to this erratum, the processor may transfer control to an unintended address.
Results are unpredictable, depending on the particular application, and can range
from no effect to the unexpected termination of the application due to an exception.
Intel has observed this erratum only in a focused testing environment. Intel has not
observed any commercially available operating system, application, or compiler that
makes use of or generates this instruction.
Workaround: If the other seven general-purpose registers are unavailable for use, and it is
necessary to do a CALL via the ESP register, first push ESP onto the stack, then
perform an indirect call using ESP (e.g., CALL [ESP]). The saved version of ESP
should be popped off the stack after the call returns.
Status: For the steppings affected see the Summary of Changes at the beginning of this
section.
E18. Memory Type Undefined for Nonmemory Operations
Specification Update 47