Intel SL3QA - Pentium III 550 MHz Processor Specification page 81

Errata
Implication: When this erratum occurs, the memory page may be as UC (rather than WC). This
may have a negative performance impact.
Workaround: None identified.
Status: For the steppings affected, see the Summary Table of Changes.
E91. Under Certain Conditions LTR (Load Task Register) Instruction May
Result in System Hang
Problem: An LTR instruction may result in a system hang if all the following conditions are met:
1. Invalid data selector of the TR (Task Register) resulting with either #GP (General
Protection Fault) or #NP (Segment Not Present Fault).
2. GDT (Global Descriptor Table) is not 8-Bytes aligned. GDT (Global Descriptor
Table) is not 8-Bytes aligned.
3. Data BP (breakpoint) is set on cache line containing the descriptor data.
Implication: This erratum may result in system hang if all conditions have been met.
erratum has not been observed in commercial operating systems or software. For
performance reasons, GDT is typically aligned to 8-Bytes.
Workaround: Software should align GDT to 8-Bytes.
Status: For the steppings affected, see the Summary Table of Changes.
E92. Loading from Memory Type USWC (Uncacheable Speculative Write
Combine) May Get Its Data Internally Forwarded From a Previous
Pending Store
Problem: A load from memory type USWC may get its data internally forwarded from a
pending store. As a result, the expected load may never be issued to the external
bus.
Implication: When this erratum occurs, a USWC Load request may be satisfied without being
observed on the external bus. There are no known usage models where this behavior
results in any negative side-effects.
Workaround: Do not use memory type USWC for memory that has read side effects.
Status: For the steppings affected, see the Summary Table of Changes.
E93. FXSAVE after FNINIT Without an Intervening FP (Floating Point)
Instruction
Instruction Operand (Data) Pointer Offset) and FDS (x87 FPU
Instruction Operand (Data) Pointer Selector)
Problem: An FXSAVE after FNINIT without an intervening FP instruction may save uninitialized
values for FDP and FDS.
Implication: When this erratum occurs, the values for FDP/FDS in the FXSAVE structure may
appear to be random values.
Specification Update
May Save Uninitialized
These values will be initialized by the first FP
Values for FDP
This
(x87 FPU
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